2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6SX Sabresd board.
6 * SPDX-License-Identifier: GPL-2.0+
13 #include "mx6_common.h"
16 #define CONFIG_SPL_LIBCOMMON_SUPPORT
17 #define CONFIG_SPL_MMC_SUPPORT
21 /* Size of malloc() pool */
22 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
24 #define CONFIG_BOARD_EARLY_INIT_F
26 #define CONFIG_MXC_UART
27 #define CONFIG_MXC_UART_BASE UART1_BASE
29 /* allow to overwrite serial and ethaddr */
30 #define CONFIG_ENV_OVERWRITE
31 #define CONFIG_CONS_INDEX 1
32 #define CONFIG_BAUDRATE 115200
34 /* Command definition */
36 #define CONFIG_EXTRA_ENV_SETTINGS \
40 "fdt_high=0xffffffff\0" \
41 "initrd_high=0xffffffff\0" \
42 "fdt_file=imx6sx-sdb.dtb\0" \
43 "fdt_addr=0x88000000\0" \
48 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
49 "mmcargs=setenv bootargs console=${console},${baudrate} " \
52 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
53 "bootscript=echo Running bootscript from mmc ...; " \
55 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
56 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
57 "mmcboot=echo Booting from mmc ...; " \
59 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
60 "if run loadfdt; then " \
61 "bootz ${loadaddr} - ${fdt_addr}; " \
63 "if test ${boot_fdt} = try; then " \
66 "echo WARN: Cannot load the DT; " \
72 "netargs=setenv bootargs console=${console},${baudrate} " \
74 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
75 "netboot=echo Booting from net ...; " \
77 "if test ${ip_dyn} = yes; then " \
78 "setenv get_cmd dhcp; " \
80 "setenv get_cmd tftp; " \
82 "${get_cmd} ${image}; " \
83 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
84 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
85 "bootz ${loadaddr} - ${fdt_addr}; " \
87 "if test ${boot_fdt} = try; then " \
90 "echo WARN: Cannot load the DT; " \
97 #define CONFIG_BOOTCOMMAND \
98 "mmc dev ${mmcdev};" \
99 "mmc dev ${mmcdev}; if mmc rescan; then " \
100 "if run loadbootscript; then " \
103 "if run loadimage; then " \
105 "else run netboot; " \
108 "else run netboot; fi"
110 /* Miscellaneous configurable options */
111 #define CONFIG_SYS_LONGHELP
112 #define CONFIG_SYS_HUSH_PARSER
113 #define CONFIG_AUTO_COMPLETE
114 #define CONFIG_SYS_CBSIZE 1024
116 #define CONFIG_SYS_MAXARGS 256
117 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
119 #define CONFIG_SYS_MEMTEST_START 0x80000000
120 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
122 #define CONFIG_CMDLINE_EDITING
123 #define CONFIG_STACKSIZE SZ_128K
125 /* Physical Memory Map */
126 #define CONFIG_NR_DRAM_BANKS 1
127 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
128 #define PHYS_SDRAM_SIZE SZ_1G
130 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
131 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
132 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
134 #define CONFIG_SYS_INIT_SP_OFFSET \
135 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
136 #define CONFIG_SYS_INIT_SP_ADDR \
137 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
139 /* MMC Configuration */
140 #define CONFIG_FSL_ESDHC
141 #define CONFIG_FSL_USDHC
142 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
145 #define CONFIG_CMD_MMC
146 #define CONFIG_GENERIC_MMC
147 #define CONFIG_BOUNCE_BUFFER
148 #define CONFIG_CMD_EXT2
149 #define CONFIG_CMD_FAT
150 #define CONFIG_DOS_PARTITION
153 #define CONFIG_CMD_I2C
154 #define CONFIG_SYS_I2C
155 #define CONFIG_SYS_I2C_MXC
156 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
157 #define CONFIG_SYS_I2C_SPEED 100000
161 #define CONFIG_POWER_I2C
162 #define CONFIG_POWER_PFUZE100
163 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
166 #define CONFIG_CMD_PING
167 #define CONFIG_CMD_DHCP
168 #define CONFIG_CMD_MII
169 #define CONFIG_CMD_NET
170 #define CONFIG_FEC_MXC
173 #define IMX_FEC_BASE ENET_BASE_ADDR
174 #define CONFIG_FEC_MXC_PHYADDR 0x1
176 #define CONFIG_FEC_XCV_TYPE RGMII
177 #define CONFIG_ETHPRIME "FEC"
179 #define CONFIG_PHYLIB
180 #define CONFIG_PHY_ATHEROS
183 #define CONFIG_CMD_USB
184 #ifdef CONFIG_CMD_USB
185 #define CONFIG_USB_EHCI
186 #define CONFIG_USB_EHCI_MX6
187 #define CONFIG_USB_STORAGE
188 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
189 #define CONFIG_USB_HOST_ETHER
190 #define CONFIG_USB_ETHER_ASIX
191 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
192 #define CONFIG_MXC_USB_FLAGS 0
193 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
196 #define CONFIG_CMD_PCI
197 #ifdef CONFIG_CMD_PCI
199 #define CONFIG_PCI_PNP
200 #define CONFIG_PCI_SCAN_SHOW
201 #define CONFIG_PCIE_IMX
202 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0)
203 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
206 #define CONFIG_IMX6_THERMAL
208 #define CONFIG_CMD_FUSE
209 #if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
210 #define CONFIG_MXC_OCOTP
213 #define CONFIG_CMD_TIME
215 #define CONFIG_FSL_QSPI
217 #ifdef CONFIG_FSL_QSPI
218 #define CONFIG_CMD_SF
219 #define CONFIG_SPI_FLASH
220 #define CONFIG_SPI_FLASH_BAR
221 #define CONFIG_SPI_FLASH_SPANSION
222 #define CONFIG_SPI_FLASH_STMICRO
223 #define CONFIG_SYS_FSL_QSPI_LE
224 #define CONFIG_SYS_FSL_QSPI_AHB
225 #ifdef CONFIG_MX6SX_SABRESD_REVA
226 #define FSL_QSPI_FLASH_SIZE SZ_16M
228 #define FSL_QSPI_FLASH_SIZE SZ_32M
230 #define FSL_QSPI_FLASH_NUM 2
233 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
234 #define CONFIG_ENV_SIZE SZ_8K
235 #define CONFIG_ENV_IS_IN_MMC
237 #define CONFIG_OF_LIBFDT
238 #define CONFIG_CMD_BOOTZ
240 #ifndef CONFIG_SYS_DCACHE_OFF
241 #define CONFIG_CMD_CACHE
244 #define CONFIG_SYS_FSL_USDHC_NUM 3
245 #if defined(CONFIG_ENV_IS_IN_MMC)
246 #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
249 #endif /* __CONFIG_H */