2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6SX Sabresd board.
6 * SPDX-License-Identifier: GPL-2.0+
13 #include "mx6_common.h"
16 #define CONFIG_SPL_LIBCOMMON_SUPPORT
17 #define CONFIG_SPL_MMC_SUPPORT
21 #define CONFIG_CMDLINE_TAG
22 #define CONFIG_SETUP_MEMORY_TAGS
23 #define CONFIG_INITRD_TAG
24 #define CONFIG_REVISION_TAG
26 /* Size of malloc() pool */
27 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
29 #define CONFIG_BOARD_EARLY_INIT_F
30 #define CONFIG_MXC_GPIO
32 #define CONFIG_MXC_UART
33 #define CONFIG_MXC_UART_BASE UART1_BASE
35 /* allow to overwrite serial and ethaddr */
36 #define CONFIG_ENV_OVERWRITE
37 #define CONFIG_CONS_INDEX 1
38 #define CONFIG_BAUDRATE 115200
40 /* Command definition */
42 #define CONFIG_BOOTDELAY 3
44 #define CONFIG_LOADADDR 0x80800000
45 #define CONFIG_SYS_TEXT_BASE 0x87800000
47 #define CONFIG_EXTRA_ENV_SETTINGS \
51 "fdt_high=0xffffffff\0" \
52 "initrd_high=0xffffffff\0" \
53 "fdt_file=imx6sx-sdb.dtb\0" \
54 "fdt_addr=0x88000000\0" \
59 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
60 "mmcargs=setenv bootargs console=${console},${baudrate} " \
63 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
64 "bootscript=echo Running bootscript from mmc ...; " \
66 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
67 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
68 "mmcboot=echo Booting from mmc ...; " \
70 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
71 "if run loadfdt; then " \
72 "bootz ${loadaddr} - ${fdt_addr}; " \
74 "if test ${boot_fdt} = try; then " \
77 "echo WARN: Cannot load the DT; " \
83 "netargs=setenv bootargs console=${console},${baudrate} " \
85 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
86 "netboot=echo Booting from net ...; " \
88 "if test ${ip_dyn} = yes; then " \
89 "setenv get_cmd dhcp; " \
91 "setenv get_cmd tftp; " \
93 "${get_cmd} ${image}; " \
94 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
95 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
96 "bootz ${loadaddr} - ${fdt_addr}; " \
98 "if test ${boot_fdt} = try; then " \
101 "echo WARN: Cannot load the DT; " \
108 #define CONFIG_BOOTCOMMAND \
109 "mmc dev ${mmcdev};" \
110 "mmc dev ${mmcdev}; if mmc rescan; then " \
111 "if run loadbootscript; then " \
114 "if run loadimage; then " \
116 "else run netboot; " \
119 "else run netboot; fi"
121 /* Miscellaneous configurable options */
122 #define CONFIG_SYS_LONGHELP
123 #define CONFIG_SYS_HUSH_PARSER
124 #define CONFIG_AUTO_COMPLETE
125 #define CONFIG_SYS_CBSIZE 1024
127 #define CONFIG_SYS_MAXARGS 256
128 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
130 #define CONFIG_SYS_MEMTEST_START 0x80000000
131 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
133 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
135 #define CONFIG_CMDLINE_EDITING
136 #define CONFIG_STACKSIZE SZ_128K
138 /* Physical Memory Map */
139 #define CONFIG_NR_DRAM_BANKS 1
140 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
141 #define PHYS_SDRAM_SIZE SZ_1G
143 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
144 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
145 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
147 #define CONFIG_SYS_INIT_SP_OFFSET \
148 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
149 #define CONFIG_SYS_INIT_SP_ADDR \
150 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
152 /* MMC Configuration */
153 #define CONFIG_FSL_ESDHC
154 #define CONFIG_FSL_USDHC
155 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
158 #define CONFIG_CMD_MMC
159 #define CONFIG_GENERIC_MMC
160 #define CONFIG_BOUNCE_BUFFER
161 #define CONFIG_CMD_EXT2
162 #define CONFIG_CMD_FAT
163 #define CONFIG_DOS_PARTITION
166 #define CONFIG_CMD_I2C
167 #define CONFIG_SYS_I2C
168 #define CONFIG_SYS_I2C_MXC
169 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
170 #define CONFIG_SYS_I2C_SPEED 100000
174 #define CONFIG_POWER_I2C
175 #define CONFIG_POWER_PFUZE100
176 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
179 #define CONFIG_CMD_PING
180 #define CONFIG_CMD_DHCP
181 #define CONFIG_CMD_MII
182 #define CONFIG_CMD_NET
183 #define CONFIG_FEC_MXC
186 #define IMX_FEC_BASE ENET_BASE_ADDR
187 #define CONFIG_FEC_MXC_PHYADDR 0x1
189 #define CONFIG_FEC_XCV_TYPE RGMII
190 #define CONFIG_ETHPRIME "FEC"
192 #define CONFIG_PHYLIB
193 #define CONFIG_PHY_ATHEROS
196 #define CONFIG_CMD_USB
197 #ifdef CONFIG_CMD_USB
198 #define CONFIG_USB_EHCI
199 #define CONFIG_USB_EHCI_MX6
200 #define CONFIG_USB_STORAGE
201 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
202 #define CONFIG_USB_HOST_ETHER
203 #define CONFIG_USB_ETHER_ASIX
204 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
205 #define CONFIG_MXC_USB_FLAGS 0
206 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
209 #define CONFIG_CMD_PCI
210 #ifdef CONFIG_CMD_PCI
212 #define CONFIG_PCI_PNP
213 #define CONFIG_PCI_SCAN_SHOW
214 #define CONFIG_PCIE_IMX
215 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0)
216 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
219 #define CONFIG_IMX6_THERMAL
221 #define CONFIG_CMD_FUSE
222 #if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
223 #define CONFIG_MXC_OCOTP
226 #define CONFIG_CMD_TIME
228 #define CONFIG_FSL_QSPI
230 #ifdef CONFIG_FSL_QSPI
231 #define CONFIG_CMD_SF
232 #define CONFIG_SPI_FLASH
233 #define CONFIG_SPI_FLASH_BAR
234 #define CONFIG_SPI_FLASH_SPANSION
235 #define CONFIG_SPI_FLASH_STMICRO
236 #define CONFIG_SYS_FSL_QSPI_LE
237 #define CONFIG_SYS_FSL_QSPI_AHB
238 #ifdef CONFIG_MX6SX_SABRESD_REVA
239 #define FSL_QSPI_FLASH_SIZE SZ_16M
241 #define FSL_QSPI_FLASH_SIZE SZ_32M
243 #define FSL_QSPI_FLASH_NUM 2
246 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
247 #define CONFIG_ENV_SIZE SZ_8K
248 #define CONFIG_ENV_IS_IN_MMC
250 #define CONFIG_OF_LIBFDT
251 #define CONFIG_CMD_BOOTZ
253 #ifndef CONFIG_SYS_DCACHE_OFF
254 #define CONFIG_CMD_CACHE
257 #define CONFIG_SYS_FSL_USDHC_NUM 3
258 #if defined(CONFIG_ENV_IS_IN_MMC)
259 #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
262 #endif /* __CONFIG_H */