2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6SX Sabreauto board.
6 * SPDX-License-Identifier: GPL-2.0+
13 #include "mx6_common.h"
16 /* Size of malloc() pool */
17 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
19 #define CONFIG_BOARD_EARLY_INIT_F
20 #define CONFIG_BOARD_LATE_INIT
22 #define CONFIG_MXC_UART
23 #define CONFIG_MXC_UART_BASE UART1_BASE
25 #define CONFIG_EXTRA_ENV_SETTINGS \
29 "fdt_high=0xffffffff\0" \
30 "initrd_high=0xffffffff\0" \
31 "fdt_file=imx6sx-sabreauto.dtb\0" \
32 "fdt_addr=0x88000000\0" \
37 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
38 "mmcargs=setenv bootargs console=${console},${baudrate} " \
41 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
42 "bootscript=echo Running bootscript from mmc ...; " \
44 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
45 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
46 "mmcboot=echo Booting from mmc ...; " \
48 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
49 "if run loadfdt; then " \
50 "bootz ${loadaddr} - ${fdt_addr}; " \
52 "if test ${boot_fdt} = try; then " \
55 "echo WARN: Cannot load the DT; " \
61 "netargs=setenv bootargs console=${console},${baudrate} " \
63 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
64 "netboot=echo Booting from net ...; " \
66 "if test ${ip_dyn} = yes; then " \
67 "setenv get_cmd dhcp; " \
69 "setenv get_cmd tftp; " \
71 "${get_cmd} ${image}; " \
72 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
73 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
74 "bootz ${loadaddr} - ${fdt_addr}; " \
76 "if test ${boot_fdt} = try; then " \
79 "echo WARN: Cannot load the DT; " \
86 #define CONFIG_BOOTCOMMAND \
87 "mmc dev ${mmcdev};" \
88 "mmc dev ${mmcdev}; if mmc rescan; then " \
89 "if run loadbootscript; then " \
92 "if run loadimage; then " \
94 "else run netboot; " \
97 "else run netboot; fi"
99 /* Miscellaneous configurable options */
100 #define CONFIG_SYS_MEMTEST_START 0x80000000
101 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
103 #define CONFIG_STACKSIZE SZ_128K
105 /* Physical Memory Map */
106 #define CONFIG_NR_DRAM_BANKS 1
107 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
108 #define PHYS_SDRAM_SIZE SZ_2G
110 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
111 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
112 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
114 #define CONFIG_SYS_INIT_SP_OFFSET \
115 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
116 #define CONFIG_SYS_INIT_SP_ADDR \
117 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
119 /* MMC Configuration */
120 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
123 #define CONFIG_CMD_I2C
124 #define CONFIG_SYS_I2C
125 #define CONFIG_SYS_I2C_MXC
126 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
127 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
128 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
129 #define CONFIG_SYS_I2C_SPEED 100000
133 #define CONFIG_POWER_I2C
134 #define CONFIG_POWER_PFUZE100
135 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
137 /* NAND flash command */
138 #define CONFIG_CMD_NAND
139 #define CONFIG_CMD_NAND_TRIMFFS
142 #define CONFIG_NAND_MXS
143 #define CONFIG_SYS_MAX_NAND_DEVICE 1
144 #define CONFIG_SYS_NAND_BASE 0x40000000
145 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
146 #define CONFIG_SYS_NAND_ONFI_DETECTION
148 /* DMA stuff, needed for GPMI/MXS NAND support */
149 #define CONFIG_APBH_DMA
150 #define CONFIG_APBH_DMA_BURST
151 #define CONFIG_APBH_DMA_BURST8
154 #define CONFIG_CMD_PING
155 #define CONFIG_CMD_DHCP
156 #define CONFIG_CMD_MII
158 #define CONFIG_FEC_MXC
161 #define IMX_FEC_BASE ENET2_BASE_ADDR
162 #define CONFIG_FEC_MXC_PHYADDR 0x0
164 #define CONFIG_FEC_XCV_TYPE RGMII
165 #define CONFIG_ETHPRIME "FEC"
167 #define CONFIG_PHYLIB
168 #define CONFIG_PHY_ATHEROS
171 #define CONFIG_CMD_USB
172 #ifdef CONFIG_CMD_USB
173 #define CONFIG_USB_EHCI
174 #define CONFIG_USB_EHCI_MX6
175 #define CONFIG_USB_STORAGE
176 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
177 #define CONFIG_USB_HOST_ETHER
178 #define CONFIG_USB_ETHER_ASIX
179 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
180 #define CONFIG_MXC_USB_FLAGS 0
181 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
184 #define CONFIG_IMX_THERMAL
186 #define CONFIG_CMD_TIME
188 #define CONFIG_FSL_QSPI
189 #ifdef CONFIG_FSL_QSPI
190 #define CONFIG_CMD_SF
191 #define CONFIG_SYS_FSL_QSPI_AHB
192 #define CONFIG_SF_DEFAULT_BUS 0
193 #define CONFIG_SF_DEFAULT_CS 0
194 #define CONFIG_SF_DEFAULT_SPEED 40000000
195 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
196 #define FSL_QSPI_FLASH_SIZE SZ_32M
197 #define FSL_QSPI_FLASH_NUM 2
200 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
201 #define CONFIG_ENV_SIZE SZ_8K
202 #define CONFIG_ENV_IS_IN_MMC
204 #define CONFIG_SYS_FSL_USDHC_NUM 2
205 #if defined(CONFIG_ENV_IS_IN_MMC)
206 #define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/
209 #define CONFIG_PCA953X
210 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
212 #endif /* __CONFIG_H */