2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6SX Sabreauto board.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "mx6_common.h"
14 /* Size of malloc() pool */
15 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
17 #define CONFIG_BOARD_EARLY_INIT_F
18 #define CONFIG_BOARD_LATE_INIT
20 #define CONFIG_MXC_UART
21 #define CONFIG_MXC_UART_BASE UART1_BASE
23 #define CONFIG_EXTRA_ENV_SETTINGS \
27 "fdt_high=0xffffffff\0" \
28 "initrd_high=0xffffffff\0" \
29 "fdt_file=imx6sx-sabreauto.dtb\0" \
30 "fdt_addr=0x88000000\0" \
35 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
36 "mmcargs=setenv bootargs console=${console},${baudrate} " \
39 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
40 "bootscript=echo Running bootscript from mmc ...; " \
42 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
43 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
44 "mmcboot=echo Booting from mmc ...; " \
46 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
47 "if run loadfdt; then " \
48 "bootz ${loadaddr} - ${fdt_addr}; " \
50 "if test ${boot_fdt} = try; then " \
53 "echo WARN: Cannot load the DT; " \
59 "netargs=setenv bootargs console=${console},${baudrate} " \
61 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
62 "netboot=echo Booting from net ...; " \
64 "if test ${ip_dyn} = yes; then " \
65 "setenv get_cmd dhcp; " \
67 "setenv get_cmd tftp; " \
69 "${get_cmd} ${image}; " \
70 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
71 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
72 "bootz ${loadaddr} - ${fdt_addr}; " \
74 "if test ${boot_fdt} = try; then " \
77 "echo WARN: Cannot load the DT; " \
84 #define CONFIG_BOOTCOMMAND \
85 "mmc dev ${mmcdev};" \
86 "mmc dev ${mmcdev}; if mmc rescan; then " \
87 "if run loadbootscript; then " \
90 "if run loadimage; then " \
92 "else run netboot; " \
95 "else run netboot; fi"
97 /* Miscellaneous configurable options */
98 #define CONFIG_SYS_MEMTEST_START 0x80000000
99 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
101 #define CONFIG_STACKSIZE SZ_128K
103 /* Physical Memory Map */
104 #define CONFIG_NR_DRAM_BANKS 1
105 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
106 #define PHYS_SDRAM_SIZE SZ_2G
108 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
109 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
110 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
112 #define CONFIG_SYS_INIT_SP_OFFSET \
113 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
114 #define CONFIG_SYS_INIT_SP_ADDR \
115 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
117 /* MMC Configuration */
118 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
121 #define CONFIG_SYS_I2C
122 #define CONFIG_SYS_I2C_MXC
123 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
124 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
125 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
126 #define CONFIG_SYS_I2C_SPEED 100000
130 #define CONFIG_POWER_I2C
131 #define CONFIG_POWER_PFUZE100
132 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
134 /* NAND flash command */
135 #define CONFIG_CMD_NAND
136 #define CONFIG_CMD_NAND_TRIMFFS
139 #define CONFIG_NAND_MXS
140 #define CONFIG_SYS_MAX_NAND_DEVICE 1
141 #define CONFIG_SYS_NAND_BASE 0x40000000
142 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
143 #define CONFIG_SYS_NAND_ONFI_DETECTION
145 /* DMA stuff, needed for GPMI/MXS NAND support */
146 #define CONFIG_APBH_DMA
147 #define CONFIG_APBH_DMA_BURST
148 #define CONFIG_APBH_DMA_BURST8
152 #define CONFIG_FEC_MXC
155 #define IMX_FEC_BASE ENET2_BASE_ADDR
156 #define CONFIG_FEC_MXC_PHYADDR 0x0
158 #define CONFIG_FEC_XCV_TYPE RGMII
159 #define CONFIG_ETHPRIME "FEC"
161 #define CONFIG_PHYLIB
162 #define CONFIG_PHY_ATHEROS
164 #ifdef CONFIG_CMD_USB
165 #define CONFIG_USB_EHCI
166 #define CONFIG_USB_EHCI_MX6
167 #define CONFIG_USB_STORAGE
168 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
169 #define CONFIG_USB_HOST_ETHER
170 #define CONFIG_USB_ETHER_ASIX
171 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
172 #define CONFIG_MXC_USB_FLAGS 0
173 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
176 #define CONFIG_IMX_THERMAL
178 #define CONFIG_FSL_QSPI
179 #ifdef CONFIG_FSL_QSPI
180 #define CONFIG_SYS_FSL_QSPI_AHB
181 #define CONFIG_SF_DEFAULT_BUS 0
182 #define CONFIG_SF_DEFAULT_CS 0
183 #define CONFIG_SF_DEFAULT_SPEED 40000000
184 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
185 #define FSL_QSPI_FLASH_SIZE SZ_32M
186 #define FSL_QSPI_FLASH_NUM 2
189 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
190 #define CONFIG_ENV_SIZE SZ_8K
191 #define CONFIG_ENV_IS_IN_MMC
193 #define CONFIG_SYS_FSL_USDHC_NUM 2
194 #if defined(CONFIG_ENV_IS_IN_MMC)
195 #define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/
198 #define CONFIG_PCA953X
199 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
201 #endif /* __CONFIG_H */