1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
5 * Configuration settings for the Freescale i.MX6SX Sabreauto board.
11 #include "mx6_common.h"
13 /* Size of malloc() pool */
14 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
16 #define CONFIG_MXC_UART_BASE UART1_BASE
18 #define CONFIG_EXTRA_ENV_SETTINGS \
22 "fdt_high=0xffffffff\0" \
23 "initrd_high=0xffffffff\0" \
24 "fdt_file=imx6sx-sabreauto.dtb\0" \
25 "fdt_addr=0x88000000\0" \
30 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
31 "mmcargs=setenv bootargs console=${console},${baudrate} " \
34 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
35 "bootscript=echo Running bootscript from mmc ...; " \
37 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
38 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
39 "mmcboot=echo Booting from mmc ...; " \
41 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
42 "if run loadfdt; then " \
43 "bootz ${loadaddr} - ${fdt_addr}; " \
45 "if test ${boot_fdt} = try; then " \
48 "echo WARN: Cannot load the DT; " \
54 "netargs=setenv bootargs console=${console},${baudrate} " \
56 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
57 "netboot=echo Booting from net ...; " \
59 "if test ${ip_dyn} = yes; then " \
60 "setenv get_cmd dhcp; " \
62 "setenv get_cmd tftp; " \
64 "${get_cmd} ${image}; " \
65 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
66 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
67 "bootz ${loadaddr} - ${fdt_addr}; " \
69 "if test ${boot_fdt} = try; then " \
72 "echo WARN: Cannot load the DT; " \
79 #define CONFIG_BOOTCOMMAND \
80 "mmc dev ${mmcdev};" \
81 "mmc dev ${mmcdev}; if mmc rescan; then " \
82 "if run loadbootscript; then " \
85 "if run loadimage; then " \
87 "else run netboot; " \
90 "else run netboot; fi"
92 /* Miscellaneous configurable options */
94 /* Physical Memory Map */
95 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
97 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
98 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
99 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
101 #define CONFIG_SYS_INIT_SP_OFFSET \
102 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
103 #define CONFIG_SYS_INIT_SP_ADDR \
104 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
106 /* MMC Configuration */
107 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
110 #define CONFIG_SYS_I2C_MXC
111 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
112 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
113 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
114 #define CONFIG_SYS_I2C_SPEED 100000
117 #define CONFIG_SYS_MAX_NAND_DEVICE 1
118 #define CONFIG_SYS_NAND_BASE 0x40000000
119 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
120 #define CONFIG_SYS_NAND_ONFI_DETECTION
122 /* DMA stuff, needed for GPMI/MXS NAND support */
126 #define CONFIG_FEC_MXC
128 #define IMX_FEC_BASE ENET2_BASE_ADDR
129 #define CONFIG_FEC_MXC_PHYADDR 0x0
131 #define CONFIG_FEC_XCV_TYPE RGMII
132 #define CONFIG_ETHPRIME "FEC"
134 #ifdef CONFIG_CMD_USB
135 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
136 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
137 #define CONFIG_MXC_USB_FLAGS 0
138 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
141 #define CONFIG_SYS_FSL_USDHC_NUM 2
143 #endif /* __CONFIG_H */