2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * Configuration settings for Freescale MX53 low cost board.
7 * SPDX-License-Identifier: GPL-2.0+
13 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
15 #include <asm/arch/imx-regs.h>
17 #define CONFIG_CMDLINE_TAG
18 #define CONFIG_SETUP_MEMORY_TAGS
19 #define CONFIG_INITRD_TAG
21 #define CONFIG_SYS_FSL_CLK
23 /* Size of malloc() pool */
24 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
26 #define CONFIG_REVISION_TAG
28 #define CONFIG_MXC_UART
29 #define CONFIG_MXC_UART_BASE UART1_BASE
32 #define CONFIG_FSL_ESDHC
33 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
34 #define CONFIG_SYS_FSL_ESDHC_NUM 2
39 #define CONFIG_FEC_MXC
40 #define IMX_FEC_BASE FEC_BASE_ADDR
41 #define CONFIG_FEC_MXC_PHYADDR 0x1F
44 #define CONFIG_USB_EHCI_MX5
45 #define CONFIG_MXC_USB_PORT 1
46 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
47 #define CONFIG_MXC_USB_FLAGS 0
50 #define CONFIG_SYS_I2C
51 #define CONFIG_SYS_I2C_MXC
52 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
53 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
54 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
58 #define CONFIG_POWER_I2C
59 #define CONFIG_DIALOG_POWER
60 #define CONFIG_POWER_FSL
61 #define CONFIG_POWER_FSL_MC13892
62 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
63 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
65 /* allow to overwrite serial and ethaddr */
66 #define CONFIG_ENV_OVERWRITE
67 #define CONFIG_CONS_INDEX 1
69 /* Command definition */
70 #define CONFIG_SUPPORT_RAW_INITRD
73 #define CONFIG_ETHPRIME "FEC0"
75 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
77 #define CONFIG_EXTRA_ENV_SETTINGS \
80 "fdt_addr=0x71000000\0" \
85 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
86 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
88 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
89 "bootscript=echo Running bootscript from mmc ...; " \
91 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
92 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
93 "mmcboot=echo Booting from mmc ...; " \
95 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
96 "if run loadfdt; then " \
97 "bootz ${loadaddr} - ${fdt_addr}; " \
99 "if test ${boot_fdt} = try; then " \
102 "echo WARN: Cannot load the DT; " \
108 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
110 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
111 "netboot=echo Booting from net ...; " \
113 "if test ${ip_dyn} = yes; then " \
114 "setenv get_cmd dhcp; " \
116 "setenv get_cmd tftp; " \
118 "${get_cmd} ${image}; " \
119 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
120 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
121 "bootz ${loadaddr} - ${fdt_addr}; " \
123 "if test ${boot_fdt} = try; then " \
126 "echo ERROR: Cannot load the DT; " \
134 #define CONFIG_BOOTCOMMAND \
135 "mmc dev ${mmcdev}; if mmc rescan; then " \
136 "if run loadbootscript; then " \
139 "if run loadimage; then " \
141 "else run netboot; " \
144 "else run netboot; fi"
146 #define CONFIG_ARP_TIMEOUT 200UL
148 /* Miscellaneous configurable options */
149 #define CONFIG_SYS_LONGHELP /* undef to save memory */
150 #define CONFIG_AUTO_COMPLETE
151 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
153 #define CONFIG_SYS_MEMTEST_START 0x70000000
154 #define CONFIG_SYS_MEMTEST_END 0x70010000
156 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
158 #define CONFIG_CMDLINE_EDITING
160 /* Physical Memory Map */
161 #define CONFIG_NR_DRAM_BANKS 2
162 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
163 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
164 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
165 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
166 #define PHYS_SDRAM_SIZE (gd->ram_size)
168 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
169 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
170 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
172 #define CONFIG_SYS_INIT_SP_OFFSET \
173 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
174 #define CONFIG_SYS_INIT_SP_ADDR \
175 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
177 /* environment organization */
178 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
179 #define CONFIG_ENV_SIZE (8 * 1024)
180 #define CONFIG_SYS_MMC_ENV_DEV 0
182 #ifdef CONFIG_CMD_SATA
183 #define CONFIG_SYS_SATA_MAX_DEVICE 1
184 #define CONFIG_DWC_AHSATA_PORT_ID 0
185 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
189 /* Framebuffer and LCD */
190 #define CONFIG_PREBOOT
191 #define CONFIG_VIDEO_IPUV3
192 #define CONFIG_VIDEO_BMP_RLE8
193 #define CONFIG_SPLASH_SCREEN
194 #define CONFIG_BMP_16BPP
195 #define CONFIG_VIDEO_LOGO
197 #endif /* __CONFIG_H */