1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * Jason Liu <r64343@freescale.com>
6 * Configuration settings for Freescale MX53 low cost board.
12 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
14 #include <asm/arch/imx-regs.h>
16 #define CONFIG_CMDLINE_TAG
17 #define CONFIG_SETUP_MEMORY_TAGS
18 #define CONFIG_INITRD_TAG
20 #define CONFIG_SYS_FSL_CLK
22 /* Size of malloc() pool */
23 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
25 #define CONFIG_REVISION_TAG
27 #define CONFIG_MXC_UART_BASE UART1_BASE
30 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
31 #define CONFIG_SYS_FSL_ESDHC_NUM 2
34 #define CONFIG_MXC_USB_PORT 1
35 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
36 #define CONFIG_MXC_USB_FLAGS 0
39 #define CONFIG_SYS_I2C_LEGACY
40 #define CONFIG_SYS_I2C_MXC
41 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
42 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
43 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
47 #define CONFIG_POWER_I2C
48 #define CONFIG_DIALOG_POWER
49 #define CONFIG_POWER_FSL
50 #define CONFIG_POWER_FSL_MC13892
51 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
52 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
54 /* Command definition */
57 #define CONFIG_ETHPRIME "FEC0"
59 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
61 #define CONFIG_EXTRA_ENV_SETTINGS \
64 "fdt_addr=0x71000000\0" \
69 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
70 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
72 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
73 "bootscript=echo Running bootscript from mmc ...; " \
75 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
76 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
77 "mmcboot=echo Booting from mmc ...; " \
79 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
80 "if run loadfdt; then " \
81 "bootz ${loadaddr} - ${fdt_addr}; " \
83 "if test ${boot_fdt} = try; then " \
86 "echo WARN: Cannot load the DT; " \
92 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
94 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
95 "netboot=echo Booting from net ...; " \
97 "if test ${ip_dyn} = yes; then " \
98 "setenv get_cmd dhcp; " \
100 "setenv get_cmd tftp; " \
102 "${get_cmd} ${image}; " \
103 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
104 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
105 "bootz ${loadaddr} - ${fdt_addr}; " \
107 "if test ${boot_fdt} = try; then " \
110 "echo ERROR: Cannot load the DT; " \
118 #define CONFIG_BOOTCOMMAND \
119 "mmc dev ${mmcdev}; if mmc rescan; then " \
120 "if run loadbootscript; then " \
123 "if run loadimage; then " \
125 "else run netboot; " \
128 "else run netboot; fi"
130 #define CONFIG_ARP_TIMEOUT 200UL
132 /* Miscellaneous configurable options */
133 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
135 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
137 /* Physical Memory Map */
138 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
139 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
140 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
141 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
142 #define PHYS_SDRAM_SIZE (gd->ram_size)
144 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
145 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
146 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
148 #define CONFIG_SYS_INIT_SP_OFFSET \
149 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
150 #define CONFIG_SYS_INIT_SP_ADDR \
151 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
153 /* Environment starts at 768k = 768 * 1024 = 786432 */
155 * Detect overlap between U-Boot image and environment area in build-time
157 * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset
158 * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
160 * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
161 * write the direct value here
163 #define CONFIG_BOARD_SIZE_LIMIT 785408
165 #ifdef CONFIG_CMD_SATA
166 #define CONFIG_SYS_SATA_MAX_DEVICE 1
167 #define CONFIG_DWC_AHSATA_PORT_ID 0
168 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
172 /* Framebuffer and LCD */
173 #define CONFIG_VIDEO_LOGO
175 #endif /* __CONFIG_H */