2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * Configuration settings for Freescale MX53 low cost board.
7 * SPDX-License-Identifier: GPL-2.0+
13 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
15 #include <asm/arch/imx-regs.h>
17 #define CONFIG_CMDLINE_TAG
18 #define CONFIG_SETUP_MEMORY_TAGS
19 #define CONFIG_INITRD_TAG
21 #define CONFIG_SYS_FSL_CLK
23 /* Size of malloc() pool */
24 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
26 #define CONFIG_MXC_GPIO
27 #define CONFIG_REVISION_TAG
29 #define CONFIG_MXC_UART
30 #define CONFIG_MXC_UART_BASE UART1_BASE
33 #define CONFIG_FSL_ESDHC
34 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
35 #define CONFIG_SYS_FSL_ESDHC_NUM 2
40 #define CONFIG_FEC_MXC
41 #define IMX_FEC_BASE FEC_BASE_ADDR
42 #define CONFIG_FEC_MXC_PHYADDR 0x1F
45 #define CONFIG_USB_EHCI_MX5
46 #define CONFIG_USB_ETHER_ASIX
47 #define CONFIG_USB_ETHER_MCS7830
48 #define CONFIG_USB_ETHER_SMSC95XX
49 #define CONFIG_MXC_USB_PORT 1
50 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
51 #define CONFIG_MXC_USB_FLAGS 0
54 #define CONFIG_SYS_I2C
55 #define CONFIG_SYS_I2C_MXC
56 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
57 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
58 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
62 #define CONFIG_POWER_I2C
63 #define CONFIG_DIALOG_POWER
64 #define CONFIG_POWER_FSL
65 #define CONFIG_POWER_FSL_MC13892
66 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
67 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
69 /* allow to overwrite serial and ethaddr */
70 #define CONFIG_ENV_OVERWRITE
71 #define CONFIG_CONS_INDEX 1
73 /* Command definition */
74 #define CONFIG_SUPPORT_RAW_INITRD
77 #define CONFIG_ETHPRIME "FEC0"
79 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
80 #define CONFIG_SYS_TEXT_BASE 0x77800000
82 #define CONFIG_EXTRA_ENV_SETTINGS \
85 "fdt_addr=0x71000000\0" \
90 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
91 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
93 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
94 "bootscript=echo Running bootscript from mmc ...; " \
96 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
97 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
98 "mmcboot=echo Booting from mmc ...; " \
100 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
101 "if run loadfdt; then " \
102 "bootz ${loadaddr} - ${fdt_addr}; " \
104 "if test ${boot_fdt} = try; then " \
107 "echo WARN: Cannot load the DT; " \
113 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
115 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
116 "netboot=echo Booting from net ...; " \
118 "if test ${ip_dyn} = yes; then " \
119 "setenv get_cmd dhcp; " \
121 "setenv get_cmd tftp; " \
123 "${get_cmd} ${image}; " \
124 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
125 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
126 "bootz ${loadaddr} - ${fdt_addr}; " \
128 "if test ${boot_fdt} = try; then " \
131 "echo ERROR: Cannot load the DT; " \
139 #define CONFIG_BOOTCOMMAND \
140 "mmc dev ${mmcdev}; if mmc rescan; then " \
141 "if run loadbootscript; then " \
144 "if run loadimage; then " \
146 "else run netboot; " \
149 "else run netboot; fi"
151 #define CONFIG_ARP_TIMEOUT 200UL
153 /* Miscellaneous configurable options */
154 #define CONFIG_SYS_LONGHELP /* undef to save memory */
155 #define CONFIG_AUTO_COMPLETE
156 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
158 #define CONFIG_SYS_MEMTEST_START 0x70000000
159 #define CONFIG_SYS_MEMTEST_END 0x70010000
161 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
163 #define CONFIG_CMDLINE_EDITING
165 /* Physical Memory Map */
166 #define CONFIG_NR_DRAM_BANKS 2
167 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
168 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
169 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
170 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
171 #define PHYS_SDRAM_SIZE (gd->ram_size)
173 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
174 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
175 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
177 #define CONFIG_SYS_INIT_SP_OFFSET \
178 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
179 #define CONFIG_SYS_INIT_SP_ADDR \
180 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
182 /* environment organization */
183 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
184 #define CONFIG_ENV_SIZE (8 * 1024)
185 #define CONFIG_SYS_MMC_ENV_DEV 0
187 #ifdef CONFIG_CMD_SATA
188 #define CONFIG_DWC_AHSATA
189 #define CONFIG_SYS_SATA_MAX_DEVICE 1
190 #define CONFIG_DWC_AHSATA_PORT_ID 0
191 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
193 #define CONFIG_LIBATA
196 /* Framebuffer and LCD */
197 #define CONFIG_PREBOOT
198 #define CONFIG_VIDEO_IPUV3
199 #define CONFIG_VIDEO_BMP_RLE8
200 #define CONFIG_SPLASH_SCREEN
201 #define CONFIG_BMP_16BPP
202 #define CONFIG_VIDEO_LOGO
203 #define CONFIG_IPUV3_CLK 200000000
205 #endif /* __CONFIG_H */