1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * Jason Liu <r64343@freescale.com>
6 * Configuration settings for Freescale MX53 low cost board.
12 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
14 #include <asm/arch/imx-regs.h>
16 #define CONFIG_CMDLINE_TAG
17 #define CONFIG_SETUP_MEMORY_TAGS
18 #define CONFIG_INITRD_TAG
20 #define CONFIG_SYS_FSL_CLK
22 /* Size of malloc() pool */
23 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
25 #define CONFIG_REVISION_TAG
27 #define CONFIG_MXC_UART
28 #define CONFIG_MXC_UART_BASE UART1_BASE
31 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
32 #define CONFIG_SYS_FSL_ESDHC_NUM 2
36 #define CONFIG_FEC_MXC
37 #define IMX_FEC_BASE FEC_BASE_ADDR
38 #define CONFIG_FEC_MXC_PHYADDR 0x1F
41 #define CONFIG_USB_EHCI_MX5
42 #define CONFIG_MXC_USB_PORT 1
43 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
44 #define CONFIG_MXC_USB_FLAGS 0
47 #define CONFIG_SYS_I2C
48 #define CONFIG_SYS_I2C_MXC
49 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
50 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
51 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
55 #define CONFIG_POWER_I2C
56 #define CONFIG_DIALOG_POWER
57 #define CONFIG_POWER_FSL
58 #define CONFIG_POWER_FSL_MC13892
59 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
60 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
62 /* allow to overwrite serial and ethaddr */
63 #define CONFIG_ENV_OVERWRITE
65 /* Command definition */
68 #define CONFIG_ETHPRIME "FEC0"
70 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
72 #define CONFIG_EXTRA_ENV_SETTINGS \
75 "fdt_addr=0x71000000\0" \
80 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
81 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
83 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
84 "bootscript=echo Running bootscript from mmc ...; " \
86 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
87 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
88 "mmcboot=echo Booting from mmc ...; " \
90 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
91 "if run loadfdt; then " \
92 "bootz ${loadaddr} - ${fdt_addr}; " \
94 "if test ${boot_fdt} = try; then " \
97 "echo WARN: Cannot load the DT; " \
103 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
105 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
106 "netboot=echo Booting from net ...; " \
108 "if test ${ip_dyn} = yes; then " \
109 "setenv get_cmd dhcp; " \
111 "setenv get_cmd tftp; " \
113 "${get_cmd} ${image}; " \
114 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
115 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
116 "bootz ${loadaddr} - ${fdt_addr}; " \
118 "if test ${boot_fdt} = try; then " \
121 "echo ERROR: Cannot load the DT; " \
129 #define CONFIG_BOOTCOMMAND \
130 "mmc dev ${mmcdev}; if mmc rescan; then " \
131 "if run loadbootscript; then " \
134 "if run loadimage; then " \
136 "else run netboot; " \
139 "else run netboot; fi"
141 #define CONFIG_ARP_TIMEOUT 200UL
143 /* Miscellaneous configurable options */
144 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
146 #define CONFIG_SYS_MEMTEST_START 0x70000000
147 #define CONFIG_SYS_MEMTEST_END 0x70010000
149 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
151 /* Physical Memory Map */
152 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
153 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
154 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
155 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
156 #define PHYS_SDRAM_SIZE (gd->ram_size)
158 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
159 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
160 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
162 #define CONFIG_SYS_INIT_SP_OFFSET \
163 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
164 #define CONFIG_SYS_INIT_SP_ADDR \
165 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
167 /* environment organization */
168 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
169 #define CONFIG_ENV_SIZE (8 * 1024)
170 #define CONFIG_SYS_MMC_ENV_DEV 0
172 #ifdef CONFIG_CMD_SATA
173 #define CONFIG_SYS_SATA_MAX_DEVICE 1
174 #define CONFIG_DWC_AHSATA_PORT_ID 0
175 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
179 /* Framebuffer and LCD */
180 #define CONFIG_PREBOOT
181 #define CONFIG_VIDEO_IPUV3
182 #define CONFIG_VIDEO_BMP_RLE8
183 #define CONFIG_SPLASH_SCREEN
184 #define CONFIG_BMP_16BPP
185 #define CONFIG_VIDEO_LOGO
187 #endif /* __CONFIG_H */