1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * Jason Liu <r64343@freescale.com>
6 * Configuration settings for Freescale MX53 low cost board.
12 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
14 #include <asm/arch/imx-regs.h>
16 #define CONFIG_CMDLINE_TAG
17 #define CONFIG_SETUP_MEMORY_TAGS
18 #define CONFIG_INITRD_TAG
20 #define CONFIG_SYS_FSL_CLK
22 /* Size of malloc() pool */
23 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
25 #define CONFIG_REVISION_TAG
27 #define CONFIG_MXC_UART
28 #define CONFIG_MXC_UART_BASE UART1_BASE
31 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
32 #define CONFIG_SYS_FSL_ESDHC_NUM 2
36 #define CONFIG_FEC_MXC
37 #define IMX_FEC_BASE FEC_BASE_ADDR
38 #define CONFIG_FEC_MXC_PHYADDR 0x1F
41 #define CONFIG_MXC_USB_PORT 1
42 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
43 #define CONFIG_MXC_USB_FLAGS 0
46 #define CONFIG_SYS_I2C
47 #define CONFIG_SYS_I2C_MXC
48 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
49 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
50 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
54 #define CONFIG_POWER_I2C
55 #define CONFIG_DIALOG_POWER
56 #define CONFIG_POWER_FSL
57 #define CONFIG_POWER_FSL_MC13892
58 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
59 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
61 /* allow to overwrite serial and ethaddr */
62 #define CONFIG_ENV_OVERWRITE
64 /* Command definition */
67 #define CONFIG_ETHPRIME "FEC0"
69 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
71 #define CONFIG_EXTRA_ENV_SETTINGS \
74 "fdt_addr=0x71000000\0" \
79 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
80 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
82 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
83 "bootscript=echo Running bootscript from mmc ...; " \
85 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
86 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
87 "mmcboot=echo Booting from mmc ...; " \
89 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
90 "if run loadfdt; then " \
91 "bootz ${loadaddr} - ${fdt_addr}; " \
93 "if test ${boot_fdt} = try; then " \
96 "echo WARN: Cannot load the DT; " \
102 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
104 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
105 "netboot=echo Booting from net ...; " \
107 "if test ${ip_dyn} = yes; then " \
108 "setenv get_cmd dhcp; " \
110 "setenv get_cmd tftp; " \
112 "${get_cmd} ${image}; " \
113 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
114 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
115 "bootz ${loadaddr} - ${fdt_addr}; " \
117 "if test ${boot_fdt} = try; then " \
120 "echo ERROR: Cannot load the DT; " \
128 #define CONFIG_BOOTCOMMAND \
129 "mmc dev ${mmcdev}; if mmc rescan; then " \
130 "if run loadbootscript; then " \
133 "if run loadimage; then " \
135 "else run netboot; " \
138 "else run netboot; fi"
140 #define CONFIG_ARP_TIMEOUT 200UL
142 /* Miscellaneous configurable options */
143 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
145 #define CONFIG_SYS_MEMTEST_START 0x70000000
146 #define CONFIG_SYS_MEMTEST_END 0x70010000
148 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
150 /* Physical Memory Map */
151 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
152 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
153 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
154 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
155 #define PHYS_SDRAM_SIZE (gd->ram_size)
157 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
158 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
159 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
161 #define CONFIG_SYS_INIT_SP_OFFSET \
162 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
163 #define CONFIG_SYS_INIT_SP_ADDR \
164 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
166 /* environment organization */
167 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
168 #define CONFIG_ENV_SIZE (8 * 1024)
169 #define CONFIG_SYS_MMC_ENV_DEV 0
171 #ifdef CONFIG_CMD_SATA
172 #define CONFIG_SYS_SATA_MAX_DEVICE 1
173 #define CONFIG_DWC_AHSATA_PORT_ID 0
174 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
178 /* Framebuffer and LCD */
179 #define CONFIG_PREBOOT
180 #define CONFIG_VIDEO_BMP_RLE8
181 #define CONFIG_SPLASH_SCREEN
182 #define CONFIG_BMP_16BPP
183 #define CONFIG_VIDEO_LOGO
185 #endif /* __CONFIG_H */