1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * Jason Liu <r64343@freescale.com>
6 * Configuration settings for Freescale MX53 low cost board.
12 #include <asm/arch/imx-regs.h>
14 #define CONFIG_MXC_UART_BASE UART1_BASE
17 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
18 #define CONFIG_SYS_FSL_ESDHC_NUM 2
21 #define CONFIG_MXC_USB_PORT 1
22 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
23 #define CONFIG_MXC_USB_FLAGS 0
26 #define CONFIG_POWER_FSL
27 #define CONFIG_POWER_FSL_MC13892
28 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
29 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
31 /* Command definition */
33 #define CONFIG_EXTRA_ENV_SETTINGS \
36 "fdt_addr=0x71000000\0" \
41 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
42 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
44 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
45 "bootscript=echo Running bootscript from mmc ...; " \
47 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
48 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
49 "mmcboot=echo Booting from mmc ...; " \
51 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
52 "if run loadfdt; then " \
53 "bootz ${loadaddr} - ${fdt_addr}; " \
55 "if test ${boot_fdt} = try; then " \
58 "echo WARN: Cannot load the DT; " \
64 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
66 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
67 "netboot=echo Booting from net ...; " \
69 "if test ${ip_dyn} = yes; then " \
70 "setenv get_cmd dhcp; " \
72 "setenv get_cmd tftp; " \
74 "${get_cmd} ${image}; " \
75 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
76 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
77 "bootz ${loadaddr} - ${fdt_addr}; " \
79 "if test ${boot_fdt} = try; then " \
82 "echo ERROR: Cannot load the DT; " \
90 /* Miscellaneous configurable options */
92 /* Physical Memory Map */
93 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
94 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
95 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
96 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
97 #define PHYS_SDRAM_SIZE (gd->ram_size)
99 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
100 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
101 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
103 #ifdef CONFIG_CMD_SATA
104 #define CONFIG_DWC_AHSATA_PORT_ID 0
105 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
109 /* Framebuffer and LCD */
111 #endif /* __CONFIG_H */