1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
4 * Patrick Bruenn <p.bruenn@beckhoff.com>
6 * Configuration settings for Beckhoff CX9020.
8 * Based on Freescale's Linux i.MX mx53loco.h file:
9 * Copyright (C) 2010-2011 Freescale Semiconductor.
15 #include <asm/arch/imx-regs.h>
17 #define CONFIG_CMDLINE_TAG
18 #define CONFIG_SETUP_MEMORY_TAGS
19 #define CONFIG_INITRD_TAG
21 #define CONFIG_SYS_FSL_CLK
23 /* Size of malloc() pool */
24 #define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
26 #define CONFIG_REVISION_TAG
28 #define CONFIG_MXC_UART_BASE UART2_BASE
30 #define CONFIG_FPGA_COUNT 1
33 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
34 #define CONFIG_SYS_FSL_ESDHC_NUM 2
36 /* bootz: zImage/initrd.img support */
40 #define CONFIG_MXC_USB_PORT 1
41 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
42 #define CONFIG_MXC_USB_FLAGS 0
44 /* allow to overwrite serial and ethaddr */
45 #define CONFIG_ENV_OVERWRITE
47 /* Command definition */
49 #define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */
51 #define BOOT_TARGET_DEVICES(func) \
57 #include <config_distro_bootcmd.h>
59 #define CONFIG_EXTRA_ENV_SETTINGS \
60 "fdt_addr_r=0x75000000\0" \
61 "pxefile_addr_r=0x73000000\0" \
62 "scriptaddr=0x74000000\0" \
63 "ramdisk_addr_r=0x80000000\0" \
64 "kernel_addr_r=0x72000000\0" \
65 "fdt_high=0xffffffff\0" \
66 "console=ttymxc1,115200\0" \
68 "stdout=serial,vidconsole\0" \
69 "stderr=serial,vidconsole\0" \
70 "fdtfile=imx53-cx9020.dtb\0" \
73 #define CONFIG_ARP_TIMEOUT 200UL
75 /* Miscellaneous configurable options */
76 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
78 #define CONFIG_SYS_MEMTEST_START 0x70000000
79 #define CONFIG_SYS_MEMTEST_END 0x70010000
81 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
83 /* Physical Memory Map */
84 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
85 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
86 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
87 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
88 #define PHYS_SDRAM_SIZE (gd->ram_size)
90 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
91 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
92 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
94 #define CONFIG_SYS_INIT_SP_OFFSET \
95 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
96 #define CONFIG_SYS_INIT_SP_ADDR \
97 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
99 /* environment organization */
100 #define CONFIG_SYS_MMC_ENV_DEV 0
102 /* Framebuffer and LCD */
103 #define CONFIG_IMX_VIDEO_SKIP
105 #endif /* __CONFIG_H */