2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * Configuration settings for the MX53ARD Freescale board.
6 * SPDX-License-Identifier: GPL-2.0+
12 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD
14 #include <asm/arch/imx-regs.h>
16 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
17 #define CONFIG_SETUP_MEMORY_TAGS
18 #define CONFIG_INITRD_TAG
19 #define CONFIG_REVISION_TAG
21 #define CONFIG_SYS_FSL_CLK
23 /* Size of malloc() pool */
24 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
26 #define CONFIG_SYS_MAX_NAND_DEVICE 1
27 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
28 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
29 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
30 #define CONFIG_SYS_NAND_LARGEPAGE
31 #define CONFIG_MXC_NAND_HWECC
32 #define CONFIG_SYS_NAND_USE_FLASH_BBT
34 #define CONFIG_MXC_UART
35 #define CONFIG_MXC_UART_BASE UART1_BASE
38 #define CONFIG_SYS_I2C
39 #define CONFIG_SYS_I2C_MXC
40 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
41 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
42 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
45 #define CONFIG_FSL_ESDHC
46 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
47 #define CONFIG_SYS_FSL_ESDHC_NUM 2
50 #define CONFIG_HAS_ETH1
53 /* allow to overwrite serial and ethaddr */
54 #define CONFIG_ENV_OVERWRITE
55 #define CONFIG_CONS_INDEX 1
57 /* Command definition */
59 #define CONFIG_ETHPRIME "smc911x"
61 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
63 #define CONFIG_EXTRA_ENV_SETTINGS \
67 "fdt_high=0xffffffff\0" \
68 "initrd_high=0xffffffff\0" \
69 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
70 "fdt_addr=0x78000000\0" \
73 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
75 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
76 "update_sd_firmware_filename=u-boot.imx\0" \
77 "update_sd_firmware=" \
78 "if test ${ip_dyn} = yes; then " \
79 "setenv get_cmd dhcp; " \
81 "setenv get_cmd tftp; " \
83 "if mmc dev ${mmcdev}; then " \
84 "if ${get_cmd} ${update_sd_firmware_filename}; then " \
85 "setexpr fw_sz ${filesize} / 0x200; " \
86 "setexpr fw_sz ${fw_sz} + 1; " \
87 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
90 "mmcargs=setenv bootargs console=${console},${baudrate} " \
93 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
94 "bootscript=echo Running bootscript from mmc ...; " \
96 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
97 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
98 "mmcboot=echo Booting from mmc ...; " \
100 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
101 "if run loadfdt; then " \
102 "bootz ${loadaddr} - ${fdt_addr}; " \
104 "if test ${boot_fdt} = try; then " \
107 "echo WARN: Cannot load the DT; " \
113 "netargs=setenv bootargs console=${console},${baudrate} " \
115 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
116 "netboot=echo Booting from net ...; " \
118 "if test ${ip_dyn} = yes; then " \
119 "setenv get_cmd dhcp; " \
121 "setenv get_cmd tftp; " \
123 "${get_cmd} ${uimage}; " \
124 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
125 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
126 "bootz ${loadaddr} - ${fdt_addr}; " \
128 "if test ${boot_fdt} = try; then " \
131 "echo WARN: Cannot load the DT; " \
138 #define CONFIG_BOOTCOMMAND \
139 "mmc dev ${mmcdev}; if mmc rescan; then " \
140 "if run loadbootscript; then " \
143 "if run loaduimage; then " \
145 "else run netboot; " \
148 "else run netboot; fi"
150 #define CONFIG_ARP_TIMEOUT 200UL
152 /* Miscellaneous configurable options */
153 #define CONFIG_SYS_LONGHELP /* undef to save memory */
154 #define CONFIG_AUTO_COMPLETE
156 #define CONFIG_SYS_MEMTEST_START 0x70000000
157 #define CONFIG_SYS_MEMTEST_END 0x70010000
159 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
161 #define CONFIG_CMDLINE_EDITING
163 /* Physical Memory Map */
164 #define CONFIG_NR_DRAM_BANKS 2
165 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
166 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
167 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
168 #define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
169 #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
171 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
172 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
173 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
175 #define CONFIG_SYS_INIT_SP_OFFSET \
176 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
177 #define CONFIG_SYS_INIT_SP_ADDR \
178 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
180 /* environment organization */
181 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
182 #define CONFIG_ENV_SIZE (8 * 1024)
183 #define CONFIG_SYS_MMC_ENV_DEV 0
185 #define MX53ARD_CS1GCR1 (CSEN | DSZ(2))
186 #define MX53ARD_CS1RCR1 (RCSN(2) | OEN (1) | RWSC(22))
187 #define MX53ARD_CS1RCR2 RBEN(2)
188 #define MX53ARD_CS1WCR1 (WCSN(2) | WEN(2) | WBEN(2) | WWSC(22))
190 #endif /* __CONFIG_H */