2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
6 * Richard Woodruff <r-woodruff2@ti.com>
7 * Kshitij Gupta <kshitij@ti.com>
9 * Configuration settings for the Freescale i.MX31 PDK board.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/imx-regs.h>
35 /* High Level Configuration Options */
36 #define CONFIG_ARM1136 /* This is an arm1136 CPU core */
37 #define CONFIG_MX31 /* in a mx31 */
38 #define CONFIG_MX31_HCLK_FREQ 26000000
39 #define CONFIG_MX31_CLK32 32768
41 #define CONFIG_DISPLAY_CPUINFO
42 #define CONFIG_DISPLAY_BOARDINFO
44 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
45 #define CONFIG_SETUP_MEMORY_TAGS
46 #define CONFIG_INITRD_TAG
48 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
50 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
51 #define CONFIG_SKIP_LOWLEVEL_INIT
55 * Size of malloc() pool
57 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
63 #define CONFIG_MXC_UART
64 #define CONFIG_MXC_UART_BASE UART1_BASE
65 #define CONFIG_HW_WATCHDOG
66 #define CONFIG_MXC_GPIO
68 #define CONFIG_HARD_SPI
69 #define CONFIG_MXC_SPI
70 #define CONFIG_DEFAULT_SPI_BUS 1
71 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
75 #define CONFIG_PMIC_SPI
76 #define CONFIG_PMIC_FSL
77 #define CONFIG_FSL_PMIC_BUS 1
78 #define CONFIG_FSL_PMIC_CS 2
79 #define CONFIG_FSL_PMIC_CLK 1000000
80 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
81 #define CONFIG_FSL_PMIC_BITLEN 32
82 #define CONFIG_RTC_MC13XXX
84 /* allow to overwrite serial and ethaddr */
85 #define CONFIG_ENV_OVERWRITE
86 #define CONFIG_CONS_INDEX 1
87 #define CONFIG_BAUDRATE 115200
88 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
90 /***********************************************************
92 ***********************************************************/
94 #include <config_cmd_default.h>
96 #define CONFIG_CMD_MII
97 #define CONFIG_CMD_PING
98 #define CONFIG_CMD_DHCP
99 #define CONFIG_CMD_SPI
100 #define CONFIG_CMD_DATE
101 #define CONFIG_CMD_NAND
102 #define CONFIG_CMD_BOOTZ
105 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
106 * that CFG_NO_FLASH is undefined).
108 #undef CONFIG_CMD_IMLS
110 #define CONFIG_BOARD_LATE_INIT
112 #define CONFIG_BOOTDELAY 3
114 #define CONFIG_EXTRA_ENV_SETTINGS \
115 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
116 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
117 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
118 "bootcmd=run bootcmd_net\0" \
119 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
120 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
121 "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \
122 "nand erase 0x0 0x40000; " \
123 "nand write 0x81000000 0x0 0x40000\0"
125 #define CONFIG_SMC911X
126 #define CONFIG_SMC911X_BASE 0xB6000000
127 #define CONFIG_SMC911X_32_BIT
130 * Miscellaneous configurable options
132 #define CONFIG_SYS_LONGHELP /* undef to save memory */
133 #define CONFIG_SYS_PROMPT "MX31PDK U-Boot > "
134 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
135 /* Print Buffer Size */
136 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
137 sizeof(CONFIG_SYS_PROMPT)+16)
138 /* max number of command args */
139 #define CONFIG_SYS_MAXARGS 16
140 /* Boot Argument Buffer Size */
141 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
143 /* memtest works on */
144 #define CONFIG_SYS_MEMTEST_START 0x80000000
145 #define CONFIG_SYS_MEMTEST_END 0x80010000
147 /* default load address */
148 #define CONFIG_SYS_LOAD_ADDR 0x81000000
150 #define CONFIG_SYS_HZ 1000
152 #define CONFIG_CMDLINE_EDITING
154 /*-----------------------------------------------------------------------
157 * The stack sizes are set up in start.S using the settings below
159 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
161 /*-----------------------------------------------------------------------
162 * Physical Memory Map
164 #define CONFIG_NR_DRAM_BANKS 1
165 #define PHYS_SDRAM_1 CSD0_BASE
166 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
167 #define CONFIG_BOARD_EARLY_INIT_F
169 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
170 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
171 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
172 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
173 GENERATED_GBL_DATA_SIZE)
174 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
175 CONFIG_SYS_GBL_DATA_OFFSET)
177 /*-----------------------------------------------------------------------
178 * FLASH and environment organization
180 /* No NOR flash present */
181 #define CONFIG_SYS_NO_FLASH
183 #define CONFIG_ENV_IS_IN_NAND
184 #define CONFIG_ENV_OFFSET 0x40000
185 #define CONFIG_ENV_OFFSET_REDUND 0x60000
186 #define CONFIG_ENV_SIZE (128 * 1024)
191 #define CONFIG_NAND_MXC
192 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
193 #define CONFIG_SYS_MAX_NAND_DEVICE 1
194 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
195 #define CONFIG_MXC_NAND_HWECC
196 #define CONFIG_SYS_NAND_LARGEPAGE
198 /* NAND configuration for the NAND_SPL */
200 /* Start copying real U-boot from the second page */
201 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
202 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
203 /* Load U-Boot to this address */
204 #define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000
205 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
207 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
208 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
209 #define CONFIG_SYS_NAND_PAGE_COUNT 64
210 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
211 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
214 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
215 #define CCM_CCMR_SETUP 0x074B0BF5
216 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
217 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \
218 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \
220 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
223 #define ESDMISC_MDDR_SETUP 0x00000004
224 #define ESDMISC_MDDR_RESET_DL 0x0000000c
225 #define ESDCFG0_MDDR_SETUP 0x006ac73a
227 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
228 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
229 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
230 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
231 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
232 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
233 #define ESDCTL_RW ESDCTL_SETTINGS
235 #endif /* __CONFIG_H */