Merge git://git.denx.de/u-boot-nand-flash
[platform/kernel/u-boot.git] / include / configs / mx31pdk.h
1 /*
2  * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
3  *
4  * (C) Copyright 2004
5  * Texas Instruments.
6  * Richard Woodruff <r-woodruff2@ti.com>
7  * Kshitij Gupta <kshitij@ti.com>
8  *
9  * Configuration settings for the Freescale i.MX31 PDK board.
10  *
11  * SPDX-License-Identifier:     GPL-2.0+
12  */
13
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16
17 #include <asm/arch/imx-regs.h>
18
19 /* High Level Configuration Options */
20 #define CONFIG_MX31                     /* This is a mx31 */
21
22 #define CONFIG_DISPLAY_CPUINFO
23 #define CONFIG_DISPLAY_BOARDINFO
24
25 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
26 #define CONFIG_SETUP_MEMORY_TAGS
27 #define CONFIG_INITRD_TAG
28
29 #define CONFIG_MACH_TYPE        MACH_TYPE_MX31_3DS
30
31 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
32 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
33 #define CONFIG_SPL_MAX_SIZE     2048
34 #define CONFIG_SPL_NAND_SUPPORT
35 #define CONFIG_SPL_LIBGENERIC_SUPPORT
36 #define CONFIG_SPL_SERIAL_SUPPORT
37
38 #define CONFIG_SPL_TEXT_BASE    0x87dc0000
39 #define CONFIG_SYS_TEXT_BASE    0x87e00000
40
41 #ifndef CONFIG_SPL_BUILD
42 #define CONFIG_SKIP_LOWLEVEL_INIT
43 #endif
44
45 /*
46  * Size of malloc() pool
47  */
48 #define CONFIG_SYS_MALLOC_LEN           (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
49
50 /*
51  * Hardware drivers
52  */
53
54 #define CONFIG_MXC_UART
55 #define CONFIG_MXC_UART_BASE    UART1_BASE
56 #define CONFIG_MXC_GPIO
57
58 #define CONFIG_HARD_SPI
59 #define CONFIG_MXC_SPI
60 #define CONFIG_DEFAULT_SPI_BUS  1
61 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
62
63 /* PMIC Controller */
64 #define CONFIG_POWER
65 #define CONFIG_POWER_SPI
66 #define CONFIG_POWER_FSL
67 #define CONFIG_FSL_PMIC_BUS     1
68 #define CONFIG_FSL_PMIC_CS      2
69 #define CONFIG_FSL_PMIC_CLK     1000000
70 #define CONFIG_FSL_PMIC_MODE    (SPI_MODE_0 | SPI_CS_HIGH)
71 #define CONFIG_FSL_PMIC_BITLEN  32
72 #define CONFIG_RTC_MC13XXX
73
74 /* allow to overwrite serial and ethaddr */
75 #define CONFIG_ENV_OVERWRITE
76 #define CONFIG_CONS_INDEX               1
77 #define CONFIG_BAUDRATE                 115200
78
79 /***********************************************************
80  * Command definition
81  ***********************************************************/
82 #define CONFIG_CMD_DATE
83 #define CONFIG_CMD_NAND
84
85 #define CONFIG_BOARD_LATE_INIT
86
87
88 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
89         "bootargs_base=setenv bootargs console=ttymxc0,115200\0"        \
90         "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "       \
91                 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"     \
92         "bootcmd=run bootcmd_net\0"                                     \
93         "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "     \
94                 "tftpboot 0x81000000 uImage-mx31; bootm\0"              \
95         "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; "           \
96                 "nand erase 0x0 0x40000; "                              \
97                 "nand write 0x81000000 0x0 0x40000\0"
98
99 #define CONFIG_SMC911X
100 #define CONFIG_SMC911X_BASE     0xB6000000
101 #define CONFIG_SMC911X_32_BIT
102
103 /*
104  * Miscellaneous configurable options
105  */
106 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
107 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
108 /* max number of command args */
109 #define CONFIG_SYS_MAXARGS      16
110 /* Boot Argument Buffer Size */
111 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
112
113 /* memtest works on */
114 #define CONFIG_SYS_MEMTEST_START        0x80000000
115 #define CONFIG_SYS_MEMTEST_END          0x80010000
116
117 /* default load address */
118 #define CONFIG_SYS_LOAD_ADDR            0x81000000
119
120 #define CONFIG_CMDLINE_EDITING
121
122 /*-----------------------------------------------------------------------
123  * Physical Memory Map
124  */
125 #define CONFIG_NR_DRAM_BANKS    1
126 #define PHYS_SDRAM_1            CSD0_BASE
127 #define PHYS_SDRAM_1_SIZE       (128 * 1024 * 1024)
128 #define CONFIG_BOARD_EARLY_INIT_F
129
130 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
131 #define CONFIG_SYS_INIT_RAM_ADDR        IRAM_BASE_ADDR
132 #define CONFIG_SYS_INIT_RAM_SIZE        IRAM_SIZE
133 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
134                                                 GENERATED_GBL_DATA_SIZE)
135 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
136                                                 CONFIG_SYS_INIT_RAM_SIZE)
137
138 /*-----------------------------------------------------------------------
139  * FLASH and environment organization
140  */
141 /* No NOR flash present */
142 #define CONFIG_SYS_NO_FLASH
143
144 #define CONFIG_ENV_IS_IN_NAND
145 #define CONFIG_ENV_OFFSET               0x40000
146 #define CONFIG_ENV_OFFSET_REDUND        0x60000
147 #define CONFIG_ENV_SIZE                 (128 * 1024)
148
149 /*
150  * NAND driver
151  */
152 #define CONFIG_NAND_MXC
153 #define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
154 #define CONFIG_SYS_MAX_NAND_DEVICE     1
155 #define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
156 #define CONFIG_MXC_NAND_HWECC
157 #define CONFIG_SYS_NAND_LARGEPAGE
158
159 /* NAND configuration for the NAND_SPL */
160
161 /* Start copying real U-Boot from the second page */
162 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
163 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x3f800
164 /* Load U-Boot to this address */
165 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
166 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
167
168 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
169 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
170 #define CONFIG_SYS_NAND_PAGE_COUNT      64
171 #define CONFIG_SYS_NAND_SIZE            (256 * 1024 * 1024)
172 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
173
174 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
175 #define CCM_CCMR_SETUP          0x074B0BF5
176 #define CCM_PDR0_SETUP_532MHZ   (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
177                                  PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
178                                  PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
179                                  PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
180 #define CCM_MPCTL_SETUP_532MHZ  (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
181                                  PLL_MFN(12))
182
183 #define ESDMISC_MDDR_SETUP      0x00000004
184 #define ESDMISC_MDDR_RESET_DL   0x0000000c
185 #define ESDCFG0_MDDR_SETUP      0x006ac73a
186
187 #define ESDCTL_ROW_COL          (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
188 #define ESDCTL_SETTINGS         (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
189                                  ESDCTL_DSIZ(2) | ESDCTL_BL(1))
190 #define ESDCTL_PRECHARGE        (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
191 #define ESDCTL_AUTOREFRESH      (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
192 #define ESDCTL_LOADMODEREG      (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
193 #define ESDCTL_RW               ESDCTL_SETTINGS
194
195 #endif /* __CONFIG_H */