include/configs/mx31pdk.h

   1 /*
   2  * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
   3  *
   4  * (C) Copyright 2004
   5  * Texas Instruments.
   6  * Richard Woodruff <r-woodruff2@ti.com>
   7  * Kshitij Gupta <kshitij@ti.com>
   8  *
   9  * Configuration settings for the Freescale i.MX31 PDK board.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 #include <asm/arch/imx-regs.h>
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_MX31                     /* This is a mx31 */
  21
  22 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
  23 #define CONFIG_SETUP_MEMORY_TAGS
  24 #define CONFIG_INITRD_TAG
  25
  26 #define CONFIG_MACH_TYPE        MACH_TYPE_MX31_3DS
  27
  28 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
  29 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  30 #define CONFIG_SPL_MAX_SIZE     2048
  31
  32 #define CONFIG_SPL_TEXT_BASE    0x87dc0000
  33 #define CONFIG_SYS_TEXT_BASE    0x87e00000
  34
  35 #ifndef CONFIG_SPL_BUILD
  36 #define CONFIG_SKIP_LOWLEVEL_INIT
  37 #endif
  38
  39 /*
  40  * Size of malloc() pool
  41  */
  42 #define CONFIG_SYS_MALLOC_LEN           (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
  43
  44 /*
  45  * Hardware drivers
  46  */
  47
  48 #define CONFIG_MXC_UART
  49 #define CONFIG_MXC_UART_BASE    UART1_BASE
  50 #define CONFIG_MXC_GPIO
  51
  52 #define CONFIG_HARD_SPI
  53 #define CONFIG_MXC_SPI
  54 #define CONFIG_DEFAULT_SPI_BUS  1
  55 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
  56
  57 /* PMIC Controller */
  58 #define CONFIG_POWER
  59 #define CONFIG_POWER_SPI
  60 #define CONFIG_POWER_FSL
  61 #define CONFIG_FSL_PMIC_BUS     1
  62 #define CONFIG_FSL_PMIC_CS      2
  63 #define CONFIG_FSL_PMIC_CLK     1000000
  64 #define CONFIG_FSL_PMIC_MODE    (SPI_MODE_0 | SPI_CS_HIGH)
  65 #define CONFIG_FSL_PMIC_BITLEN  32
  66 #define CONFIG_RTC_MC13XXX
  67
  68 /* allow to overwrite serial and ethaddr */
  69 #define CONFIG_ENV_OVERWRITE
  70 #define CONFIG_CONS_INDEX               1
  71
  72 /***********************************************************
  73  * Command definition
  74  ***********************************************************/
  75 #define CONFIG_CMD_DATE
  76 #define CONFIG_CMD_NAND
  77
  78
  79 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  80         "bootargs_base=setenv bootargs console=ttymxc0,115200\0"        \
  81         "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "       \
  82                 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"     \
  83         "bootcmd=run bootcmd_net\0"                                     \
  84         "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "     \
  85                 "tftpboot 0x81000000 uImage-mx31; bootm\0"              \
  86         "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; "           \
  87                 "nand erase 0x0 0x40000; "                              \
  88                 "nand write 0x81000000 0x0 0x40000\0"
  89
  90 #define CONFIG_SMC911X
  91 #define CONFIG_SMC911X_BASE     0xB6000000
  92 #define CONFIG_SMC911X_32_BIT
  93
  94 /*
  95  * Miscellaneous configurable options
  96  */
  97 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
  98 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
  99 /* max number of command args */
 100 #define CONFIG_SYS_MAXARGS      16
 101 /* Boot Argument Buffer Size */
 102 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 103
 104 /* memtest works on */
 105 #define CONFIG_SYS_MEMTEST_START        0x80000000
 106 #define CONFIG_SYS_MEMTEST_END          0x80010000
 107
 108 /* default load address */
 109 #define CONFIG_SYS_LOAD_ADDR            0x81000000
 110
 111 #define CONFIG_CMDLINE_EDITING
 112
 113 /*-----------------------------------------------------------------------
 114  * Physical Memory Map
 115  */
 116 #define CONFIG_NR_DRAM_BANKS    1
 117 #define PHYS_SDRAM_1            CSD0_BASE
 118 #define PHYS_SDRAM_1_SIZE       (128 * 1024 * 1024)
 119
 120 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 121 #define CONFIG_SYS_INIT_RAM_ADDR        IRAM_BASE_ADDR
 122 #define CONFIG_SYS_INIT_RAM_SIZE        IRAM_SIZE
 123 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 124                                                 GENERATED_GBL_DATA_SIZE)
 125 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
 126                                                 CONFIG_SYS_INIT_RAM_SIZE)
 127
 128 /*
 129  * environment organization
 130  */
 131 #define CONFIG_ENV_IS_IN_NAND
 132 #define CONFIG_ENV_OFFSET               0x40000
 133 #define CONFIG_ENV_OFFSET_REDUND        0x60000
 134 #define CONFIG_ENV_SIZE                 (128 * 1024)
 135
 136 /*
 137  * NAND driver
 138  */
 139 #define CONFIG_NAND_MXC
 140 #define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
 141 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 142 #define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
 143 #define CONFIG_MXC_NAND_HWECC
 144 #define CONFIG_SYS_NAND_LARGEPAGE
 145
 146 /* NAND configuration for the NAND_SPL */
 147
 148 /* Start copying real U-Boot from the second page */
 149 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 150 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x3f800
 151 /* Load U-Boot to this address */
 152 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 153 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 154
 155 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
 156 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 157 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 158 #define CONFIG_SYS_NAND_SIZE            (256 * 1024 * 1024)
 159 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 160
 161 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
 162 #define CCM_CCMR_SETUP          0x074B0BF5
 163 #define CCM_PDR0_SETUP_532MHZ   (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
 164                                  PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
 165                                  PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
 166                                  PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
 167 #define CCM_MPCTL_SETUP_532MHZ  (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
 168                                  PLL_MFN(12))
 169
 170 #define ESDMISC_MDDR_SETUP      0x00000004
 171 #define ESDMISC_MDDR_RESET_DL   0x0000000c
 172 #define ESDCFG0_MDDR_SETUP      0x006ac73a
 173
 174 #define ESDCTL_ROW_COL          (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
 175 #define ESDCTL_SETTINGS         (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
 176                                  ESDCTL_DSIZ(2) | ESDCTL_BL(1))
 177 #define ESDCTL_PRECHARGE        (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
 178 #define ESDCTL_AUTOREFRESH      (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
 179 #define ESDCTL_LOADMODEREG      (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
 180 #define ESDCTL_RW               ESDCTL_SETTINGS
 181
 182 #endif /* __CONFIG_H */