2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
6 * Richard Woodruff <r-woodruff2@ti.com>
7 * Kshitij Gupta <kshitij@ti.com>
9 * Configuration settings for the Freescale i.MX31 PDK board.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/imx-regs.h>
35 /* High Level Configuration Options */
36 #define CONFIG_ARM1136 /* This is an arm1136 CPU core */
37 #define CONFIG_MX31 /* in a mx31 */
39 #define CONFIG_DISPLAY_CPUINFO
40 #define CONFIG_DISPLAY_BOARDINFO
42 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
43 #define CONFIG_SETUP_MEMORY_TAGS
44 #define CONFIG_INITRD_TAG
46 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
50 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
51 #define CONFIG_SPL_MAX_SIZE 2048
52 #define CONFIG_SPL_NAND_SUPPORT
53 #define CONFIG_SPL_LIBGENERIC_SUPPORT
55 #define CONFIG_SPL_TEXT_BASE 0x87dc0000
56 #define CONFIG_SYS_TEXT_BASE 0x87e00000
58 #ifndef CONFIG_SPL_BUILD
59 #define CONFIG_SKIP_LOWLEVEL_INIT
63 * Size of malloc() pool
65 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
71 #define CONFIG_MXC_UART
72 #define CONFIG_MXC_UART_BASE UART1_BASE
73 #define CONFIG_MXC_GPIO
75 #define CONFIG_HARD_SPI
76 #define CONFIG_MXC_SPI
77 #define CONFIG_DEFAULT_SPI_BUS 1
78 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
82 #define CONFIG_POWER_SPI
83 #define CONFIG_POWER_FSL
84 #define CONFIG_FSL_PMIC_BUS 1
85 #define CONFIG_FSL_PMIC_CS 2
86 #define CONFIG_FSL_PMIC_CLK 1000000
87 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
88 #define CONFIG_FSL_PMIC_BITLEN 32
89 #define CONFIG_RTC_MC13XXX
91 /* allow to overwrite serial and ethaddr */
92 #define CONFIG_ENV_OVERWRITE
93 #define CONFIG_CONS_INDEX 1
94 #define CONFIG_BAUDRATE 115200
96 /***********************************************************
98 ***********************************************************/
100 #include <config_cmd_default.h>
102 #define CONFIG_CMD_MII
103 #define CONFIG_CMD_PING
104 #define CONFIG_CMD_DHCP
105 #define CONFIG_CMD_SPI
106 #define CONFIG_CMD_DATE
107 #define CONFIG_CMD_NAND
108 #define CONFIG_CMD_BOOTZ
111 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
112 * that CFG_NO_FLASH is undefined).
114 #undef CONFIG_CMD_IMLS
116 #define CONFIG_BOARD_LATE_INIT
118 #define CONFIG_BOOTDELAY 1
120 #define CONFIG_EXTRA_ENV_SETTINGS \
121 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
122 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
123 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
124 "bootcmd=run bootcmd_net\0" \
125 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
126 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
127 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
128 "nand erase 0x0 0x40000; " \
129 "nand write 0x81000000 0x0 0x40000\0"
131 #define CONFIG_SMC911X
132 #define CONFIG_SMC911X_BASE 0xB6000000
133 #define CONFIG_SMC911X_32_BIT
136 * Miscellaneous configurable options
138 #define CONFIG_SYS_LONGHELP /* undef to save memory */
139 #define CONFIG_SYS_PROMPT "MX31PDK U-Boot > "
140 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
141 /* Print Buffer Size */
142 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
143 sizeof(CONFIG_SYS_PROMPT)+16)
144 /* max number of command args */
145 #define CONFIG_SYS_MAXARGS 16
146 /* Boot Argument Buffer Size */
147 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
149 /* memtest works on */
150 #define CONFIG_SYS_MEMTEST_START 0x80000000
151 #define CONFIG_SYS_MEMTEST_END 0x80010000
153 /* default load address */
154 #define CONFIG_SYS_LOAD_ADDR 0x81000000
156 #define CONFIG_SYS_HZ 1000
158 #define CONFIG_CMDLINE_EDITING
160 /*-----------------------------------------------------------------------
161 * Physical Memory Map
163 #define CONFIG_NR_DRAM_BANKS 1
164 #define PHYS_SDRAM_1 CSD0_BASE
165 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
166 #define CONFIG_BOARD_EARLY_INIT_F
168 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
169 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
170 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
171 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
172 GENERATED_GBL_DATA_SIZE)
173 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
174 CONFIG_SYS_INIT_RAM_SIZE)
176 /*-----------------------------------------------------------------------
177 * FLASH and environment organization
179 /* No NOR flash present */
180 #define CONFIG_SYS_NO_FLASH
182 #define CONFIG_ENV_IS_IN_NAND
183 #define CONFIG_ENV_OFFSET 0x40000
184 #define CONFIG_ENV_OFFSET_REDUND 0x60000
185 #define CONFIG_ENV_SIZE (128 * 1024)
190 #define CONFIG_NAND_MXC
191 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
192 #define CONFIG_SYS_MAX_NAND_DEVICE 1
193 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
194 #define CONFIG_MXC_NAND_HWECC
195 #define CONFIG_SYS_NAND_LARGEPAGE
197 /* NAND configuration for the NAND_SPL */
199 /* Start copying real U-boot from the second page */
200 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
201 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
202 /* Load U-Boot to this address */
203 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
204 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
206 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
207 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
208 #define CONFIG_SYS_NAND_PAGE_COUNT 64
209 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
210 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
213 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
214 #define CCM_CCMR_SETUP 0x074B0BF5
215 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
216 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
217 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
218 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
219 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
222 #define ESDMISC_MDDR_SETUP 0x00000004
223 #define ESDMISC_MDDR_RESET_DL 0x0000000c
224 #define ESDCFG0_MDDR_SETUP 0x006ac73a
226 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
227 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
228 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
229 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
230 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
231 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
232 #define ESDCTL_RW ESDCTL_SETTINGS
234 #endif /* __CONFIG_H */