2bb24a1545e396e855354c06780ff2f4a93ecd07
[platform/kernel/u-boot.git] / include / configs / mx31pdk.h
1 /*
2  * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
3  *
4  * (C) Copyright 2004
5  * Texas Instruments.
6  * Richard Woodruff <r-woodruff2@ti.com>
7  * Kshitij Gupta <kshitij@ti.com>
8  *
9  * Configuration settings for the Freescale i.MX31 PDK board.
10  *
11  * SPDX-License-Identifier:     GPL-2.0+
12  */
13
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16
17 #include <asm/arch/imx-regs.h>
18
19 /* High Level Configuration Options */
20 #define CONFIG_MX31                     /* This is a mx31 */
21
22 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
23 #define CONFIG_SETUP_MEMORY_TAGS
24 #define CONFIG_INITRD_TAG
25
26 #define CONFIG_MACH_TYPE        MACH_TYPE_MX31_3DS
27
28 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
29 #define CONFIG_SPL_MAX_SIZE     2048
30
31 #define CONFIG_SPL_TEXT_BASE    0x87dc0000
32 #define CONFIG_SYS_TEXT_BASE    0x87e00000
33
34 #ifndef CONFIG_SPL_BUILD
35 #define CONFIG_SKIP_LOWLEVEL_INIT
36 #endif
37
38 /*
39  * Size of malloc() pool
40  */
41 #define CONFIG_SYS_MALLOC_LEN           (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
42
43 /*
44  * Hardware drivers
45  */
46
47 #define CONFIG_MXC_UART
48 #define CONFIG_MXC_UART_BASE    UART1_BASE
49 #define CONFIG_MXC_GPIO
50
51 #define CONFIG_HARD_SPI
52 #define CONFIG_MXC_SPI
53 #define CONFIG_DEFAULT_SPI_BUS  1
54 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
55
56 /* PMIC Controller */
57 #define CONFIG_POWER
58 #define CONFIG_POWER_SPI
59 #define CONFIG_POWER_FSL
60 #define CONFIG_FSL_PMIC_BUS     1
61 #define CONFIG_FSL_PMIC_CS      2
62 #define CONFIG_FSL_PMIC_CLK     1000000
63 #define CONFIG_FSL_PMIC_MODE    (SPI_MODE_0 | SPI_CS_HIGH)
64 #define CONFIG_FSL_PMIC_BITLEN  32
65 #define CONFIG_RTC_MC13XXX
66
67 /* allow to overwrite serial and ethaddr */
68 #define CONFIG_ENV_OVERWRITE
69 #define CONFIG_CONS_INDEX               1
70
71 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
72         "bootargs_base=setenv bootargs console=ttymxc0,115200\0"        \
73         "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "       \
74                 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"     \
75         "bootcmd=run bootcmd_net\0"                                     \
76         "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "     \
77                 "tftpboot 0x81000000 uImage-mx31; bootm\0"              \
78         "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; "           \
79                 "nand erase 0x0 0x40000; "                              \
80                 "nand write 0x81000000 0x0 0x40000\0"
81
82 #define CONFIG_SMC911X
83 #define CONFIG_SMC911X_BASE     0xB6000000
84 #define CONFIG_SMC911X_32_BIT
85
86 /*
87  * Miscellaneous configurable options
88  */
89 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
90 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
91 /* max number of command args */
92 #define CONFIG_SYS_MAXARGS      16
93 /* Boot Argument Buffer Size */
94 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
95
96 /* memtest works on */
97 #define CONFIG_SYS_MEMTEST_START        0x80000000
98 #define CONFIG_SYS_MEMTEST_END          0x80010000
99
100 /* default load address */
101 #define CONFIG_SYS_LOAD_ADDR            0x81000000
102
103 #define CONFIG_CMDLINE_EDITING
104
105 /*-----------------------------------------------------------------------
106  * Physical Memory Map
107  */
108 #define CONFIG_NR_DRAM_BANKS    1
109 #define PHYS_SDRAM_1            CSD0_BASE
110 #define PHYS_SDRAM_1_SIZE       (128 * 1024 * 1024)
111
112 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
113 #define CONFIG_SYS_INIT_RAM_ADDR        IRAM_BASE_ADDR
114 #define CONFIG_SYS_INIT_RAM_SIZE        IRAM_SIZE
115 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
116                                                 GENERATED_GBL_DATA_SIZE)
117 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
118                                                 CONFIG_SYS_INIT_RAM_SIZE)
119
120 /*
121  * environment organization
122  */
123 #define CONFIG_ENV_OFFSET               0x40000
124 #define CONFIG_ENV_OFFSET_REDUND        0x60000
125 #define CONFIG_ENV_SIZE                 (128 * 1024)
126
127 /*
128  * NAND driver
129  */
130 #define CONFIG_NAND_MXC
131 #define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
132 #define CONFIG_SYS_MAX_NAND_DEVICE     1
133 #define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
134 #define CONFIG_MXC_NAND_HWECC
135 #define CONFIG_SYS_NAND_LARGEPAGE
136
137 /* NAND configuration for the NAND_SPL */
138
139 /* Start copying real U-Boot from the second page */
140 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
141 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x3f800
142 /* Load U-Boot to this address */
143 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
144 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
145
146 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
147 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
148 #define CONFIG_SYS_NAND_PAGE_COUNT      64
149 #define CONFIG_SYS_NAND_SIZE            (256 * 1024 * 1024)
150 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
151
152 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
153 #define CCM_CCMR_SETUP          0x074B0BF5
154 #define CCM_PDR0_SETUP_532MHZ   (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
155                                  PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
156                                  PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
157                                  PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
158 #define CCM_MPCTL_SETUP_532MHZ  (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
159                                  PLL_MFN(12))
160
161 #define ESDMISC_MDDR_SETUP      0x00000004
162 #define ESDMISC_MDDR_RESET_DL   0x0000000c
163 #define ESDCFG0_MDDR_SETUP      0x006ac73a
164
165 #define ESDCTL_ROW_COL          (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
166 #define ESDCTL_SETTINGS         (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
167                                  ESDCTL_DSIZ(2) | ESDCTL_BL(1))
168 #define ESDCTL_PRECHARGE        (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
169 #define ESDCTL_AUTOREFRESH      (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
170 #define ESDCTL_LOADMODEREG      (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
171 #define ESDCTL_RW               ESDCTL_SETTINGS
172
173 #endif /* __CONFIG_H */