1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Based on vendor support provided by AVNET Embedded
5 * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
6 * Copyright 2021 General Electric Company
7 * Copyright 2021 Collabora Ltd.
10 #ifndef __MSC_SM2S_IMX8MP_H
11 #define __MSC_SM2S_IMX8MP_H
13 #include <linux/sizes.h>
14 #include <linux/stringify.h>
15 #include <asm/arch/imx-regs.h>
17 #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
19 #if defined(CONFIG_CMD_NET)
20 #define CONFIG_FEC_MXC_PHYADDR 1
21 #define PHY_ANEG_TIMEOUT 20000
24 #ifndef CONFIG_SPL_BUILD
25 #define BOOT_TARGET_DEVICES(func) \
29 #include <config_distro_bootcmd.h>
32 /* Initial environment variables */
33 #define CONFIG_EXTRA_ENV_SETTINGS \
35 "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
36 "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
38 "console=ttymxc1,115200\0" \
39 "fdt_addr_r=0x43000000\0" \
41 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
42 "initrd_addr=0x43800000\0" \
43 "bootm_size=0x10000000\0" \
45 "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
47 /* Link Definitions */
49 #define CFG_SYS_INIT_RAM_ADDR 0x40000000
50 #define CFG_SYS_INIT_RAM_SIZE 0x80000
52 #define CFG_SYS_SDRAM_BASE 0x40000000
53 #define PHYS_SDRAM 0x40000000
54 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
55 #define PHYS_SDRAM_2 0xc0000000
56 #define PHYS_SDRAM_2_SIZE 0x0
58 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
60 #define CFG_SYS_FSL_USDHC_NUM 2
61 #define CFG_SYS_FSL_ESDHC_ADDR 0