2 * (C) Copyright 2007 Czech Technical University.
4 * Michal SIMEK <monstr@seznam.cz>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include "../board/xilinx/ml401/xparameters.h"
30 #define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
31 #define CONFIG_ML401 1 /* ML401 Board */
34 #define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
35 #define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
36 #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
38 /* setting reset address */
39 //#define CFG_RESET_ADDRESS TEXT_BASE
42 #define CONFIG_EMACLITE 1
43 #define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
47 #define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
49 /* interrupt controller */
51 #define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
52 #define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
56 #define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
57 #define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
58 #define FREQUENCE XILINX_CLOCK_FREQ
59 #define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
62 * memory layout - Example
63 * TEXT_BASE = 0x1200_0000;
64 * CFG_SRAM_BASE = 0x1000_0000;
65 * CFG_SRAM_SIZE = 0x0400_0000;
67 * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
68 * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
69 * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
71 * 0x1000_0000 CFG_SDRAM_BASE
73 * 0x1200_0000 TEXT_BASE
79 * 0x13F7_F000 CFG_MALLOC_BASE
80 * MALLOC_AREA 256kB Alloc
81 * 0x11FB_F000 CFG_MONITOR_BASE
82 * MONITOR_CODE 256kB Env
83 * 0x13FF_F000 CFG_GBL_DATA_OFFSET
84 * GLOBAL_DATA 4kB bd, gd
85 * 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
88 /* ddr sdram - main memory */
89 #define CFG_SDRAM_BASE XILINX_RAM_START
90 #define CFG_SDRAM_SIZE XILINX_RAM_SIZE
91 #define CFG_MEMTEST_START CFG_SDRAM_BASE
92 #define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
95 #define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
96 /* start of global data */
97 #define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
101 #define CFG_MONITOR_LEN SIZE
102 #define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
103 #define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
104 #define CFG_MALLOC_LEN SIZE
105 #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
108 #define CFG_INIT_SP_OFFSET CFG_MONITOR_BASE
114 #define CFG_FLASH_BASE XILINX_FLASH_START
115 #define CFG_FLASH_SIZE XILINX_FLASH_SIZE
116 #define CFG_FLASH_CFI 1
117 #define CFG_FLASH_CFI_DRIVER 1
118 #define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
119 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
120 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
121 #define CFG_FLASH_PROTECTION /* hardware flash protection */
124 #define CFG_ENV_IS_NOWHERE 1
125 #define CFG_ENV_SIZE 0x1000
126 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
129 #define CFG_ENV_IS_IN_FLASH 1
130 #define CFG_ENV_ADDR 0x40000
131 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
132 #define CFG_ENV_SIZE 0x2000
133 #endif /* !RAMBOOT */
136 #define CFG_NO_FLASH 1
137 #define CFG_ENV_IS_NOWHERE 1
138 #define CFG_ENV_SIZE 0x1000
139 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
140 #define CFG_FLASH_PROTECTION /* hardware flash protection */
145 #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
148 CFG_CMD_AUTOSCRIPT |\
167 #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
170 CFG_CMD_AUTOSCRIPT |\
194 #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
197 CFG_CMD_AUTOSCRIPT |\
212 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
213 #include <cmd_confdefs.h>
215 #if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
216 /* JFFS2 partitions */
217 #define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */
218 #define MTDIDS_DEFAULT "nor0=ml401-0"
220 /* default mtd partition table */
221 #define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
222 "256k(env),3m(kernel),1m(romfs),"\
223 "1m(cramfs),-(jffs2)"
226 /* Miscellaneous configurable options */
227 #define CFG_PROMPT "U-Boot-mONStR> "
228 #define CFG_CBSIZE 512 /* size of console buffer */
229 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
230 #define CFG_MAXARGS 15 /* max number of command args */
232 #define CFG_LOAD_ADDR 0x12000000 /* default load address */
234 #define CONFIG_BOOTDELAY 30
235 #define CONFIG_BOOTARGS "root=romfs"
236 #define CONFIG_HOSTNAME "ml401"
237 #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
238 #define CONFIG_IPADDR 192.168.0.3
239 #define CONFIG_SERVERIP 192.168.0.5
240 #define CONFIG_GATEWAYIP 192.168.0.1
241 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
243 /* architecture dependent code */
244 #define CFG_USR_EXCEP /* user exception */
248 #define CONFIG_SYSTEMACE
249 /* #define DEBUG_SYSTEMACE */
250 #define SYSTEMACE_CONFIG_FPGA
251 #define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
252 #define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
253 #define CONFIG_DOS_PARTITION
255 #define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
257 #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
259 "mtdparts=mtdparts=ml401-0:"\
260 "256k(u-boot),256k(env),3m(kernel),"\
261 "1m(romfs),1m(cramfs),-(jffs2)\0"
263 #endif /* __CONFIG_H */