2 * (C) Copyright 2007-2010 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "../board/xilinx/microblaze-generic/xparameters.h"
15 #define CONFIG_MICROBLAZE 1
16 #define MICROBLAZE_V5 1
18 /* Open Firmware DTS */
19 #define CONFIG_OF_CONTROL 1
20 #define CONFIG_OF_EMBED 1
21 #define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic
23 /* linear and spi flash memory */
24 #ifdef XILINX_FLASH_START
27 #undef RAMENV /* hold environment in flash */
29 #ifdef XILINX_SPI_FLASH_BASEADDR
32 #undef RAMENV /* hold environment in flash */
36 #define RAMENV /* hold environment in RAM */
41 #ifdef XILINX_UARTLITE_BASEADDR
42 # define CONFIG_XILINX_UARTLITE
43 # define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
44 # define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
45 # define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
46 # define CONSOLE_ARG "console=console=ttyUL0,115200\0"
47 #elif XILINX_UART16550_BASEADDR
48 # define CONFIG_SYS_NS16550 1
49 # define CONFIG_SYS_NS16550_SERIAL
50 # if defined(__MICROBLAZEEL__)
51 # define CONFIG_SYS_NS16550_REG_SIZE -4
53 # define CONFIG_SYS_NS16550_REG_SIZE 4
55 # define CONFIG_CONS_INDEX 1
56 # define CONFIG_SYS_NS16550_COM1 \
57 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
58 # define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
59 # define CONFIG_BAUDRATE 115200
61 /* The following table includes the supported baudrates */
62 # define CONFIG_SYS_BAUDRATE_TABLE \
63 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
64 # define CONSOLE_ARG "console=console=ttyS0,115200\0"
66 # error Undefined uart
69 /* setting reset address */
70 /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
73 #undef CONFIG_SYS_ENET
74 #if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL)
75 # define CONFIG_XILINX_EMACLITE 1
76 # define CONFIG_SYS_ENET
78 #if defined(XILINX_LLTEMAC_BASEADDR)
79 # define CONFIG_XILINX_LL_TEMAC 1
80 # define CONFIG_SYS_ENET
82 #if defined(XILINX_AXIEMAC_BASEADDR)
83 # define CONFIG_XILINX_AXIEMAC 1
84 # define CONFIG_SYS_ENET
90 #ifdef XILINX_GPIO_BASEADDR
91 # define CONFIG_XILINX_GPIO
92 # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
95 /* interrupt controller */
96 #ifdef XILINX_INTC_BASEADDR
97 # define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
98 # define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
102 #if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
103 # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
104 # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
108 #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
109 # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
110 # define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
111 # define CONFIG_HW_WATCHDOG
112 # define CONFIG_XILINX_TB_WATCHDOG
116 * memory layout - Example
117 * CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk
118 * CONFIG_SYS_SRAM_BASE = 0x1000_0000;
119 * CONFIG_SYS_SRAM_SIZE = 0x0400_0000; 64MB
121 * CONFIG_SYS_MONITOR_LEN = 0x40000
122 * CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
124 * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
125 * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
126 * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
128 * 0x1000_0000 CONFIG_SYS_SDRAM_BASE
131 * 0x1200_0000 CONFIG_SYS_TEXT_BASE
137 * 0x13EF_F000 CONFIG_SYS_MALLOC_BASE
138 * MALLOC_AREA 768kB Alloc
139 * 0x13FB_F000 CONFIG_SYS_MONITOR_BASE
140 * MONITOR_CODE 256kB Env
141 * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET
142 * GLOBAL_DATA 4kB bd, gd
143 * 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
146 /* ddr sdram - main memory */
147 #define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
148 #define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
149 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
150 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
153 /* start of global data */
154 #define CONFIG_SYS_GBL_DATA_OFFSET \
155 (CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)
159 #define CONFIG_SYS_MONITOR_LEN SIZE
160 #define CONFIG_SYS_MONITOR_BASE \
161 (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
162 - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
163 #define CONFIG_SYS_MONITOR_END \
164 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
165 #define CONFIG_SYS_MALLOC_LEN (SIZE * 3)
166 #define CONFIG_SYS_MALLOC_BASE \
167 (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
170 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE
173 * CFI flash memory layout - Example
174 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
175 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
177 * SECT_SIZE = 0x20000; 128kB is one sector
178 * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
180 * 0x2200_0000 CONFIG_SYS_FLASH_BASE
182 * 0x2204_0000 CONFIG_ENV_ADDR
186 * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
191 # define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
192 # define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
193 # define CONFIG_SYS_FLASH_CFI 1
194 # define CONFIG_FLASH_CFI_DRIVER 1
196 # define CONFIG_SYS_FLASH_EMPTY_INFO 1
197 /* max number of memory banks */
198 # define CONFIG_SYS_MAX_FLASH_BANKS 1
199 /* max number of sectors on one chip */
200 # define CONFIG_SYS_MAX_FLASH_SECT 512
201 /* hardware flash protection */
202 # define CONFIG_SYS_FLASH_PROTECTION
203 /* use buffered writes (20x faster) */
204 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
206 # define CONFIG_ENV_IS_NOWHERE 1
207 # define CONFIG_ENV_SIZE 0x1000
208 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
210 # else /* FLASH && !RAMENV */
211 # define CONFIG_ENV_IS_IN_FLASH 1
212 /* 128K(one sector) for env */
213 # define CONFIG_ENV_SECT_SIZE 0x20000
214 # define CONFIG_ENV_ADDR \
215 (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
216 # define CONFIG_ENV_SIZE 0x20000
217 # endif /* FLASH && !RAMBOOT */
221 # define CONFIG_SYS_NO_FLASH 1
222 # define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
223 # define CONFIG_XILINX_SPI 1
224 # define CONFIG_SPI 1
225 # define CONFIG_SPI_FLASH 1
226 # define CONFIG_SPI_FLASH_STMICRO 1
227 # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
228 # define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
229 # define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
232 # define CONFIG_ENV_IS_NOWHERE 1
233 # define CONFIG_ENV_SIZE 0x1000
234 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
236 # else /* SPIFLASH && !RAMENV */
237 # define CONFIG_ENV_IS_IN_SPI_FLASH 1
238 # define CONFIG_ENV_SPI_MODE SPI_MODE_3
239 # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
240 # define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
241 /* 128K(two sectors) for env */
242 # define CONFIG_ENV_SECT_SIZE 0x10000
243 # define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
244 /* Warning: adjust the offset in respect of other flash content and size */
245 # define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
246 # endif /* SPIFLASH && !RAMBOOT */
247 #else /* !SPIFLASH */
250 # define CONFIG_SYS_NO_FLASH 1
251 # define CONFIG_ENV_IS_NOWHERE 1
252 # define CONFIG_ENV_SIZE 0x1000
253 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
254 #endif /* !SPIFLASH */
258 #ifdef XILINX_SYSACE_BASEADDR
259 # define CONFIG_SYSTEMACE
260 /* #define DEBUG_SYSTEMACE */
261 # define SYSTEMACE_CONFIG_FPGA
262 # define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
263 # define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
264 # define CONFIG_DOS_PARTITION
267 #if defined(XILINX_USE_ICACHE)
268 # define CONFIG_ICACHE
270 # undef CONFIG_ICACHE
273 #if defined(XILINX_USE_DCACHE)
274 # define CONFIG_DCACHE
276 # undef CONFIG_DCACHE
279 #ifndef XILINX_DCACHE_BYTE_SIZE
280 #define XILINX_DCACHE_BYTE_SIZE 32768
286 #define CONFIG_BOOTP_BOOTFILESIZE
287 #define CONFIG_BOOTP_BOOTPATH
288 #define CONFIG_BOOTP_GATEWAY
289 #define CONFIG_BOOTP_HOSTNAME
292 * Command line configuration.
294 #include <config_cmd_default.h>
296 #define CONFIG_CMD_ASKENV
297 #define CONFIG_CMD_IRQ
298 #define CONFIG_CMD_MFSL
299 #define CONFIG_CMD_ECHO
300 #define CONFIG_CMD_GPIO
302 #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
303 # define CONFIG_CMD_CACHE
305 # undef CONFIG_CMD_CACHE
308 #ifndef CONFIG_SYS_ENET
309 # undef CONFIG_CMD_NET
310 # undef CONFIG_CMD_NFS
312 # define CONFIG_CMD_PING
313 # define CONFIG_CMD_DHCP
314 # define CONFIG_CMD_TFTPPUT
317 #if defined(CONFIG_SYSTEMACE)
318 # define CONFIG_CMD_EXT2
319 # define CONFIG_CMD_FAT
323 # define CONFIG_CMD_ECHO
324 # define CONFIG_CMD_FLASH
325 # define CONFIG_CMD_IMLS
326 # define CONFIG_CMD_JFFS2
327 # define CONFIG_CMD_UBI
328 # undef CONFIG_CMD_UBIFS
330 # if !defined(RAMENV)
331 # define CONFIG_CMD_SAVEENV
332 # define CONFIG_CMD_SAVES
336 #if defined(SPIFLASH)
337 # define CONFIG_CMD_SF
339 # if !defined(RAMENV)
340 # define CONFIG_CMD_SAVEENV
341 # define CONFIG_CMD_SAVES
344 # undef CONFIG_CMD_IMLS
345 # undef CONFIG_CMD_FLASH
346 # undef CONFIG_CMD_JFFS2
347 # undef CONFIG_CMD_UBI
348 # undef CONFIG_CMD_UBIFS
352 #if defined(CONFIG_CMD_JFFS2)
353 # define CONFIG_MTD_PARTITIONS
356 #if defined(CONFIG_CMD_UBIFS)
357 # define CONFIG_CMD_UBI
361 #if defined(CONFIG_CMD_UBI)
362 # define CONFIG_MTD_PARTITIONS
363 # define CONFIG_RBTREE
366 #if defined(CONFIG_MTD_PARTITIONS)
368 #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
369 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
370 #define CONFIG_FLASH_CFI_MTD
371 #define MTDIDS_DEFAULT "nor0=flash-0"
373 /* default mtd partition table */
374 #define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
375 "256k(env),3m(kernel),1m(romfs),"\
376 "1m(cramfs),-(jffs2)"
379 /* Miscellaneous configurable options */
380 #define CONFIG_SYS_PROMPT "U-Boot-mONStR> "
381 /* size of console buffer */
382 #define CONFIG_SYS_CBSIZE 512
383 /* print buffer size */
384 #define CONFIG_SYS_PBSIZE \
385 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
386 /* max number of command args */
387 #define CONFIG_SYS_MAXARGS 15
388 #define CONFIG_SYS_LONGHELP
389 /* default load address */
390 #define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
392 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
393 #define CONFIG_BOOTARGS "root=romfs"
394 #define CONFIG_HOSTNAME XILINX_BOARD_NAME
395 #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
396 #define CONFIG_IPADDR 192.168.0.3
397 #define CONFIG_SERVERIP 192.168.0.5
398 #define CONFIG_GATEWAYIP 192.168.0.1
399 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
401 /* architecture dependent code */
402 #define CONFIG_SYS_USR_EXCEP /* user exception */
404 #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
406 #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
408 "mtdparts=mtdparts=flash-0:"\
409 "256k(u-boot),256k(env),3m(kernel),"\
410 "1m(romfs),1m(cramfs),-(jffs2)\0"\
411 "nc=setenv stdout nc;"\
412 "setenv stdin nc\0" \
413 "serial=setenv stdout serial;"\
414 "setenv stdin serial\0"
416 #define CONFIG_CMDLINE_EDITING
418 #define CONFIG_NETCONSOLE
419 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
421 /* Use the HUSH parser */
422 #define CONFIG_SYS_HUSH_PARSER
424 /* Enable flat device tree support */
427 #define CONFIG_OF_LIBFDT 1
429 #if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
430 # define CONFIG_MII 1
431 # define CONFIG_CMD_MII 1
432 # define CONFIG_PHY_GIGE 1
433 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
434 # define CONFIG_PHYLIB 1
435 # define CONFIG_PHY_ATHEROS 1
436 # define CONFIG_PHY_BROADCOM 1
437 # define CONFIG_PHY_DAVICOM 1
438 # define CONFIG_PHY_LXT 1
439 # define CONFIG_PHY_MARVELL 1
440 # define CONFIG_PHY_MICREL 1
441 # define CONFIG_PHY_NATSEMI 1
442 # define CONFIG_PHY_REALTEK 1
443 # define CONFIG_PHY_VITESSE 1
446 # undef CONFIG_CMD_MII
447 # undef CONFIG_PHYLIB
452 #define CONFIG_CMD_SPL
453 #define CONFIG_SPL_FRAMEWORK
454 #define CONFIG_SPL_LIBCOMMON_SUPPORT
455 #define CONFIG_SPL_LIBGENERIC_SUPPORT
456 #define CONFIG_SPL_SERIAL_SUPPORT
457 #define CONFIG_SPL_BOARD_INIT
459 #define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
461 #define CONFIG_SPL_RAM_DEVICE
462 #define CONFIG_SPL_NOR_SUPPORT
464 /* for booting directly linux */
465 #define CONFIG_SPL_OS_BOOT
467 #define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
469 #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
471 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
474 /* SP location before relocation, must use scratch RAM */
476 #define CONFIG_SYS_INIT_RAM_ADDR 0x0
477 /* BRAM size - will be generated */
478 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
479 /* Stack pointer prior relocation, must situated at on-chip RAM */
480 #define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \
481 CONFIG_SYS_INIT_RAM_SIZE - \
482 GENERATED_GBL_DATA_SIZE)
484 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100
487 * The main reason to do it in this way is that MALLOC_START
488 * can't be defined - common/spl/spl.c
490 #if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
491 # define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \
492 CONFIG_SYS_SPL_MALLOC_SIZE)
493 # define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START
495 # define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END
498 /* Just for sure that there is a space for stack */
499 #define CONFIG_SPL_STACK_SIZE 0x100
501 #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
502 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
504 #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
505 CONFIG_SYS_INIT_RAM_ADDR - \
506 GENERATED_GBL_DATA_SIZE - \
507 CONFIG_SYS_SPL_MALLOC_SIZE - \
508 CONFIG_SPL_STACK_SIZE)
510 #endif /* __CONFIG_H */