3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37 #define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
38 #define CONFIG_HOSTNAME mgsuvd
40 /* include common defines/options for all Keymile boards */
41 #include "keymile-common.h"
43 #define CONFIG_8xx_GCLK_FREQ 66000000
45 #define CONFIG_SYS_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
46 #define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0
47 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
48 #define CONFIG_SYS_SMC_RXBUFLEN 128
49 #define CONFIG_SYS_MAXIDLE 10
51 #define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation, the
52 * default value is not working */
54 #define BOOTFLASH_START F0000000
55 #define CONFIG_PRAM 512 /* protected RAM [KBytes] */
57 #define CONFIG_PREBOOT "echo;" \
58 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
61 #define BOOTFLASH_START F0000000
62 #define CONFIG_PRAM 512 /* protected RAM [KBytes] */
64 #define CONFIG_ENV_IVM "EEprom_ivm=pca9544a:70:4 \0"
66 #define CONFIG_EXTRA_ENV_SETTINGS \
68 "rootpath=/opt/eldk/ppc_8xx\0" \
69 "addcon=setenv bootargs ${bootargs} " \
70 "console=ttyCPM0,${baudrate}\0" \
71 "mtdids=nor0=app \0" \
72 "mtdparts=mtdparts=app:384k(u-boot),128k(env),128k(envred)," \
73 "128k(free),1536k(esw0),8704k(rootfs0),1536k(esw1)," \
74 "2432k(rootfs1),640k(var),768k(cfg)\0" \
75 "partition=nor0,9 \0" \
76 "new_env=prot off F0060000 F009FFFF; era F0060000 F009FFFF \0" \
80 #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
82 #define CONFIG_TIMESTAMP /* but print image timestmps */
85 * Low Level Configuration Settings
86 * (address mappings, register initial values, etc.)
87 * You should know what you are doing if you make changes here.
89 /*-----------------------------------------------------------------------
90 * Internal Memory Mapped Register
92 #define CONFIG_SYS_IMMR 0xFFF00000
94 /*-----------------------------------------------------------------------
95 * Definitions for initial stack pointer and data area (in DPRAM)
97 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
98 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
99 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
100 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
101 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
103 /*-----------------------------------------------------------------------
104 * Start addresses for the final memory configuration
105 * (Set up by the startup code)
106 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
108 #define CONFIG_SYS_SDRAM_BASE 0x00000000
109 #define CONFIG_SYS_FLASH_BASE 0xf0000000
110 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
111 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
112 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
115 * For booting Linux, the board info and command line data
116 * have to be in the first 8 MB of memory, since this is
117 * the maximum mapped by the Linux kernel during initialization.
119 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
121 /*-----------------------------------------------------------------------
124 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
125 #define CONFIG_SYS_FLASH_SIZE 32
126 #define CONFIG_SYS_FLASH_CFI
127 #define CONFIG_FLASH_CFI_DRIVER
128 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
131 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
132 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
134 #define CONFIG_ENV_IS_IN_FLASH 1
135 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
136 #define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
137 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
139 /* Address and size of Redundant Environment Sector */
140 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
141 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
142 #define CONFIG_ENV_BUFFER_PRINT 1
144 /*-----------------------------------------------------------------------
145 * Cache Configuration
147 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
148 #if defined(CONFIG_CMD_KGDB)
149 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
152 /*-----------------------------------------------------------------------
153 * SYPCR - System Protection Control 11-9
154 * SYPCR can only be written once after reset!
155 *-----------------------------------------------------------------------
156 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
158 #define CONFIG_SYS_SYPCR 0xffffff89
160 /*-----------------------------------------------------------------------
161 * SIUMCR - SIU Module Configuration 11-6
162 *-----------------------------------------------------------------------
164 #define CONFIG_SYS_SIUMCR 0x00610480
166 /*-----------------------------------------------------------------------
167 * TBSCR - Time Base Status and Control 11-26
168 *-----------------------------------------------------------------------
169 * Clear Reference Interrupt Status, Timebase freezing enabled
171 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
173 /*-----------------------------------------------------------------------
174 * PISCR - Periodic Interrupt Status and Control 11-31
175 *-----------------------------------------------------------------------
176 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
178 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
180 /*-----------------------------------------------------------------------
181 * SCCR - System Clock and reset Control Register 15-27
182 *-----------------------------------------------------------------------
183 * Set clock output, timebase and RTC source and divider,
184 * power management and some other internal clocks
186 #define SCCR_MASK 0x01800000
187 #define CONFIG_SYS_SCCR 0x01800000
189 #define CONFIG_SYS_DER 0
192 * Init Memory Controller:
194 * BR0/1 and OR0/1 (FLASH)
197 #define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
199 /* used to re-map FLASH both when starting from SRAM or FLASH:
200 * restrict access enough to keep SRAM working (if any)
201 * but not too much to meddle with FLASH accesses
203 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
204 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
207 * FLASH timing: Default value of OR0 after reset
209 #define CONFIG_SYS_OR0_PRELIM 0xfe000954
210 #define CONFIG_SYS_BR0_PRELIM 0xf0000401
213 * BR1 and OR1 (SDRAM)
216 #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
217 #define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
219 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
220 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
222 #define CONFIG_SYS_OR1_PRELIM 0xfc000800
223 #define CONFIG_SYS_BR1_PRELIM (0x000000C0 | 0x01)
225 #define CONFIG_SYS_MPTPR 0x0200
226 /* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
227 1 Write loop Cycle (not used), 1 Timer Loop Cycle */
228 #define CONFIG_SYS_MBMR 0x10964111
229 #define CONFIG_SYS_MAR 0x00000088
232 * 4096 Rows from SDRAM example configuration
233 * 1000 factor s -> ms
234 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
235 * 4 Number of refresh cycles per period
236 * 64 Refresh cycle in ms per number of rows
238 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
240 /* GPIO/PIGGY on CS3 initialization values
242 #define CONFIG_SYS_PIGGY_BASE (0x30000000)
243 #define CONFIG_SYS_OR3_PRELIM (0xfe000d24)
244 #define CONFIG_SYS_BR3_PRELIM (0x30000401)
247 * Internal Definitions
251 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
252 #define BOOTFLAG_WARM 0x02 /* Software reboot */
254 #define CONFIG_SCC3_ENET
255 #define CONFIG_ETHPRIME "SCC ETHERNET"
256 #define CONFIG_HAS_ETH0
258 /* pass open firmware flat tree */
259 #define CONFIG_OF_LIBFDT 1
260 #define CONFIG_OF_BOARD_SETUP 1
262 #define OF_STDOUT_PATH "/soc/cpm/serial@a80"
264 /* enable I2C and select the hardware/software driver */
265 #undef CONFIG_HARD_I2C /* I2C with hardware support */
266 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
267 #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
268 #define CONFIG_SYS_I2C_SLAVE 0x7F
269 #define I2C_SOFT_DECLARATIONS
272 * Software (bit-bang) I2C driver configuration
274 #define I2C_BASE_DIR ((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
275 #define I2C_BASE_PORT ((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
279 #define SDA_CONF 0x1000
280 #define SCL_CONF 0x2000
282 #define I2C_ACTIVE do {} while (0)
283 #define I2C_TRISTATE do {} while (0)
284 #define I2C_READ ((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
285 #define I2C_SDA(bit) if(bit) { \
286 clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
288 clrbits(8, I2C_BASE_PORT, SDA_BIT); \
289 setbits(be16, I2C_BASE_DIR, SDA_CONF); \
291 #define I2C_SCL(bit) if(bit) { \
292 clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
294 clrbits(8, I2C_BASE_PORT, SCL_BIT); \
295 setbits(be16, I2C_BASE_DIR, SCL_CONF); \
297 #define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
299 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
301 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
302 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
303 #define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
304 #define CONFIG_SYS_DTT_MAX_TEMP 70
305 #define CONFIG_SYS_DTT_LOW_TEMP -30
306 #define CONFIG_SYS_DTT_HYSTERESIS 3
307 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
309 #define MTDIDS_DEFAULT "nor0=app"
310 #define MTDPARTS_DEFAULT ( \
311 "mtdparts=app:384k(u-boot),128k(env),128k(envred),128k(free)," \
312 "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)")
314 #endif /* __CONFIG_H */