1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * (C) Copyright 2009-2015
8 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
9 * esd electronic system design gmbh <www.esd.eu>
11 * Configuation settings for the esd MEESC board.
18 * SoC must be defined first, before hardware.h is included.
19 * In this case SoC is defined in boards.cfg.
21 #include <asm/hardware.h>
24 * Warning: changing CONFIG_SYS_TEXT_BASE requires
25 * adapting the initial boot program.
26 * Since the linker has to swallow that define, we must use a pure
30 /* ARM asynchronous clock */
31 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
32 #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
34 /* Misc CPU related */
35 #define CONFIG_SKIP_LOWLEVEL_INIT
36 #define CONFIG_ARCH_CPU_INIT
37 #define CONFIG_SETUP_MEMORY_TAGS
38 #define CONFIG_INITRD_TAG
39 #define CONFIG_SERIAL_TAG
40 #define CONFIG_REVISION_TAG
41 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
50 #define CONFIG_BOOTP_BOOTFILESIZE
53 * SDRAM: 1 bank, min 32, max 128 MB
54 * Initialized before u-boot gets started.
56 #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
57 #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
59 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
60 #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
62 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
63 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
64 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
67 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
68 * leaving the correct space for initial global data structure above
69 * that address while providing maximum stack area below.
71 #define CONFIG_SYS_INIT_SP_ADDR \
72 (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
75 #ifdef CONFIG_CMD_NAND
76 # define CONFIG_SYS_MAX_NAND_DEVICE 1
77 # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
78 # define CONFIG_SYS_NAND_DBW_8
79 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
80 # define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
81 # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
82 # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
88 #define CONFIG_NET_RETRY_COUNT 20
89 #undef CONFIG_RESET_PHY_R
91 /* hw-controller addresses */
92 #define CONFIG_ET1100_BASE 0x70000000
94 #ifdef CONFIG_SYS_USE_DATAFLASH
96 /* bootstrap + u-boot + env in dataflash on CS0 */
97 #define CONFIG_ENV_OFFSET 0x4200
98 #define CONFIG_ENV_SIZE 0x4200
99 #define CONFIG_ENV_SECT_SIZE 0x210
101 #elif CONFIG_SYS_USE_NANDFLASH
103 /* bootstrap + u-boot + env + linux in nandflash */
104 # define CONFIG_ENV_OFFSET 0xC0000
105 # define CONFIG_ENV_SIZE 0x20000
109 #define CONFIG_SYS_CBSIZE 512
112 * Size of malloc() pool
114 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \