2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 /*************************************************************************
10 * (c) 2005 esd gmbh Hannover
14 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
16 *************************************************************************/
22 * High Level Configuration Options
26 #define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
27 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
28 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
29 #define CONFIG_MECP5200 1 /* ... on MECP5200 board */
30 #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
32 #ifndef CONFIG_SYS_TEXT_BASE
33 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
36 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
38 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
41 * Serial console configuration
43 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
45 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
47 #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
49 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
52 #if 0 /* test-only !!! */
53 #define CONFIG_EEPRO100 1
54 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
55 #define CONFIG_NS8382X 1
59 #define CONFIG_MAC_PARTITION
60 #define CONFIG_DOS_PARTITION
64 #define CONFIG_USB_OHCI
65 #define CONFIG_USB_STORAGE
72 #define CONFIG_BOOTP_BOOTFILESIZE
73 #define CONFIG_BOOTP_BOOTPATH
74 #define CONFIG_BOOTP_GATEWAY
75 #define CONFIG_BOOTP_HOSTNAME
79 * Command line configuration.
81 #include <config_cmd_default.h>
83 #define CONFIG_CMD_EEPROM
84 #define CONFIG_CMD_FAT
85 #define CONFIG_CMD_EXT2
86 #define CONFIG_CMD_I2C
87 #define CONFIG_CMD_IDE
88 #define CONFIG_CMD_BSP
89 #define CONFIG_CMD_ELF
92 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
93 # define CONFIG_SYS_LOWBOOT 1
94 # define CONFIG_SYS_LOWBOOT16 1
96 #if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
97 # define CONFIG_SYS_LOWBOOT 1
98 # define CONFIG_SYS_LOWBOOT08 1
104 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
106 #define CONFIG_PREBOOT "echo;" \
107 "echo Welcome to CBX-CPU5200 (mecp5200);" \
110 #undef CONFIG_BOOTARGS
112 #define CONFIG_EXTRA_ENV_SETTINGS \
114 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
115 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
116 "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
117 "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
118 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
119 "loadaddr=01000000\0" \
120 "serverip=192.168.2.99\0" \
121 "gatewayip=10.0.0.79\0" \
123 "target=mecp5200.esd\0" \
124 "script=mecp5200.bat\0" \
125 "image=/tftpboot/vxWorks_mecp5200\0" \
126 "ipaddr=10.0.13.196\0" \
127 "netmask=255.255.0.0\0" \
130 #define CONFIG_BOOTCOMMAND "run flash_vxworks0"
133 * IPB Bus clocking configuration.
135 #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
139 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
140 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
142 #define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
143 #define CONFIG_SYS_I2C_SLAVE 0x7F
146 * EEPROM configuration
148 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
150 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
151 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
152 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1
154 * Flash configuration
156 #define CONFIG_SYS_FLASH_BASE 0xFFC00000
157 #define CONFIG_SYS_FLASH_SIZE 0x00400000
158 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000)
159 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
160 #define CONFIG_SYS_MAX_FLASH_SECT 512
162 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
163 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
166 * Environment settings
168 #if 1 /* test-only */
169 #define CONFIG_ENV_IS_IN_FLASH 1
170 #define CONFIG_ENV_SIZE 0x10000
171 #define CONFIG_ENV_SECT_SIZE 0x10000
172 #define CONFIG_ENV_OVERWRITE 1
174 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
175 #define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
176 #define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/
177 /* total size of a CAT24WC32 is 8192 bytes */
178 #define CONFIG_ENV_OVERWRITE 1
181 #define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
182 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
183 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
185 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
187 #define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */
188 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
189 #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
195 #define CONFIG_SYS_MBAR 0xF0000000
196 #define CONFIG_SYS_SDRAM_BASE 0x00000000
197 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
199 /* Use SRAM until RAM will be available */
200 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
201 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
204 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
205 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
208 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
209 # define CONFIG_SYS_RAMBOOT 1
212 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
213 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
214 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
217 * Ethernet configuration
219 #define CONFIG_MPC5xxx_FEC 1
220 #define CONFIG_MPC5xxx_FEC_MII100
222 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
224 /* #define CONFIG_MPC5xxx_FEC_MII10 */
225 #define CONFIG_PHY_ADDR 0x00
226 #define CONFIG_UDP_CHECKSUM 1
232 #define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
235 * Miscellaneous configurable options
237 #define CONFIG_SYS_LONGHELP /* undef to save memory */
238 #if defined(CONFIG_CMD_KGDB)
239 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
241 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
243 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
244 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
245 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
247 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
248 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
250 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
252 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
254 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
255 #if defined(CONFIG_CMD_KGDB)
256 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
260 * Various low-level settings
262 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
263 #define CONFIG_SYS_HID0_FINAL HID0_ICE
265 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
266 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
267 #define CONFIG_SYS_BOOTCS_CFG 0x00085d00
269 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
270 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
272 #define CONFIG_SYS_CS1_START 0xfd000000
273 #define CONFIG_SYS_CS1_SIZE 0x00010000
274 #define CONFIG_SYS_CS1_CFG 0x10101410
276 #define CONFIG_SYS_CS_BURST 0x00000000
277 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
279 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
281 /*-----------------------------------------------------------------------
283 *-----------------------------------------------------------------------
285 #define CONFIG_USB_CLOCK 0x0001BBBB
286 #define CONFIG_USB_CONFIG 0x00001000
288 /*-----------------------------------------------------------------------
289 * IDE/ATA stuff Supports IDE harddisk
290 *-----------------------------------------------------------------------
293 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
295 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
296 #undef CONFIG_IDE_LED /* LED for ide not supported */
298 #define CONFIG_IDE_RESET /* reset for ide supported */
299 #define CONFIG_IDE_PREINIT
301 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
302 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
304 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
306 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
308 /* Offset for data I/O */
309 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
311 /* Offset for normal register accesses */
312 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
314 /* Offset for alternate registers */
315 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
317 /* Interval between registers */
318 #define CONFIG_SYS_ATA_STRIDE 4
320 #endif /* __CONFIG_H */