2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
4 * Based on omap3_evm_config.h
6 * SPDX-License-Identifier: GPL-2.0+
13 * High Level Configuration Options
16 #define CONFIG_MACH_TYPE MACH_TYPE_MCX
18 #include <asm/arch/cpu.h> /* get chip and board defs */
19 #include <asm/arch/omap.h>
22 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
23 * and older u-boot.bin with the new U-Boot SPL.
25 #define CONFIG_SYS_TEXT_BASE 0x80008000
28 #define V_OSCK 26000000 /* Clock output from T2 */
29 #define V_SCLK (V_OSCK >> 1)
31 #define CONFIG_MISC_INIT_R
33 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
34 #define CONFIG_SETUP_MEMORY_TAGS
35 #define CONFIG_INITRD_TAG
36 #define CONFIG_REVISION_TAG
39 * Size of malloc() pool
41 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
42 #define CONFIG_SYS_MALLOC_LEN (1024 << 10)
46 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
53 * NS16550 Configuration
55 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
57 #define CONFIG_SYS_NS16550_SERIAL
58 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
59 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
62 * select serial console configuration
64 #define CONFIG_CONS_INDEX 3
65 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
66 #define CONFIG_SERIAL3 3 /* UART3 */
68 /* allow to overwrite serial and ethaddr */
69 #define CONFIG_ENV_OVERWRITE
70 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
74 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
76 /* commands to include */
78 #define CONFIG_MTD_PARTITIONS
79 #define CONFIG_MTD_DEVICE
81 #define CONFIG_SYS_I2C
82 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
83 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
86 #define CONFIG_RTC_DS1337
87 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
92 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
94 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
98 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
100 #define CONFIG_JFFS2_NAND
101 /* nand device jffs2 lives on */
102 #define CONFIG_JFFS2_DEV "nand0"
103 /* start of jffs2 partition */
104 #define CONFIG_JFFS2_PART_OFFSET 0x680000
105 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
107 /* Environment information */
109 #define CONFIG_BOOTFILE "uImage"
111 /* Setup MTD for NAND on the SOM */
113 #define CONFIG_HOSTNAME mcx
114 #define CONFIG_EXTRA_ENV_SETTINGS \
115 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
116 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
117 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
118 "addfb=setenv bootargs ${bootargs} vram=6M " \
119 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
120 "addip_sta=setenv bootargs ${bootargs} " \
121 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
122 "${netmask}:${hostname}:eth0:off\0" \
123 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
124 "addip=if test -n ${ipdyn};then run addip_dyn;" \
125 "else run addip_sta;fi\0" \
126 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
127 "addtty=setenv bootargs ${bootargs} " \
128 "console=${consoledev},${baudrate}\0" \
129 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
130 "baudrate=115200\0" \
131 "consoledev=ttyO2\0" \
132 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
133 "loadaddr=0x82000000\0" \
134 "load=tftp ${loadaddr} ${u-boot}\0" \
135 "load_k=tftp ${loadaddr} ${bootfile}\0" \
136 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
137 "loadmlo=tftp ${loadaddr} ${mlo}\0" \
138 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
139 "mmcargs=root=/dev/mmcblk0p2 rw " \
140 "rootfstype=ext3 rootwait\0" \
141 "mmcboot=echo Booting from mmc ...; " \
143 "run addip addtty addmtd addfb addeth addmisc;" \
145 "bootm ${loadaddr}\0" \
146 "net_nfs=run load_k; " \
148 "run addip addtty addmtd addfb addeth addmisc;" \
149 "bootm ${loadaddr}\0" \
150 "nfsargs=setenv bootargs root=/dev/nfs rw " \
151 "nfsroot=${serverip}:${rootpath}\0" \
152 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
153 "uboot_addr=0x80000\0" \
154 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
155 "nand write ${loadaddr} ${uboot_addr} 80000\0" \
156 "updatemlo=nandecc hw;nand erase 0 20000;" \
157 "nand write ${loadaddr} 0 20000\0" \
158 "upd=if run load;then echo Updating u-boot;if run update;" \
159 "then echo U-Boot updated;" \
160 "else echo Error updating u-boot !;" \
161 "echo Board without bootloader !!;" \
163 "else echo U-Boot not downloaded..exiting;fi\0" \
164 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
165 "bootscript=echo Running bootscript from mmc ...; " \
166 "source ${loadaddr}\0" \
167 "nandargs=setenv bootargs ubi.mtd=7 " \
168 "root=ubi0:rootfs rootfstype=ubifs\0" \
169 "nandboot=echo Booting from nand ...; " \
171 "ubi part nand0,4;" \
172 "ubi readvol ${loadaddr} kernel;" \
173 "run addtty addmtd addfb addeth addmisc;" \
174 "bootm ${loadaddr}\0" \
175 "preboot=ubi part nand0,7;" \
176 "ubi readvol ${loadaddr} splash;" \
177 "bmp display ${loadaddr};" \
179 "swupdate_args=setenv bootargs root=/dev/ram " \
180 "quiet loglevel=1 " \
181 "consoleblank=0 ${swupdate_misc}\0" \
182 "swupdate=echo Running Sw-Update...;" \
183 "if printenv mtdparts;then echo Starting SwUpdate...; " \
184 "else mtdparts default;fi; " \
185 "ubi part nand0,5;" \
186 "ubi readvol 0x82000000 kernel_recovery;" \
187 "ubi part nand0,6;" \
188 "ubi readvol 0x84000000 fs_recovery;" \
189 "run swupdate_args; " \
190 "setenv bootargs ${bootargs} " \
192 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
193 "omapdss.def_disp=lcd;" \
194 "bootm 0x82000000 0x84000000\0" \
195 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
196 "then source 82000000;else run nandboot;fi\0"
198 #define CONFIG_AUTO_COMPLETE
199 #define CONFIG_CMDLINE_EDITING
202 * Miscellaneous configurable options
204 #define CONFIG_SYS_LONGHELP /* undef to save memory */
205 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
206 /* Boot Argument Buffer Size */
207 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
208 /* memtest works on */
209 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
210 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
211 0x01F00000) /* 31MB */
213 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
215 #define CONFIG_PREBOOT
218 * AM3517 has 12 GP timers, they can be driven by the system clock
219 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
220 * This rate is divided by a local divisor.
222 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
223 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
226 * Physical Memory Map
228 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
229 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
230 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
233 * FLASH and environment organization
236 /* **** PISMO SUPPORT *** */
238 /* Redundant Environment */
239 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
240 #define CONFIG_ENV_OFFSET 0x180000
241 #define CONFIG_ENV_ADDR 0x180000
242 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
243 2 * CONFIG_SYS_ENV_SECT_SIZE)
244 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
246 /* Flash banks JFFS2 should use */
247 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
248 CONFIG_SYS_MAX_NAND_DEVICE)
249 #define CONFIG_SYS_JFFS2_MEM_NAND
250 /* use flash_info[2] */
251 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
252 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
254 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
255 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
256 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
257 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
258 CONFIG_SYS_INIT_RAM_SIZE - \
259 GENERATED_GBL_DATA_SIZE)
261 /* Defines for SPL */
262 #define CONFIG_SPL_FRAMEWORK
264 #define CONFIG_SPL_NAND_BASE
265 #define CONFIG_SPL_NAND_DRIVERS
266 #define CONFIG_SPL_NAND_ECC
268 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
269 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
270 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
272 /* move malloc and bss high to prevent clashing with the main image */
273 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
274 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
275 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
276 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
278 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
279 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
281 /* NAND boot config */
282 #define CONFIG_SYS_NAND_PAGE_COUNT 64
283 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
284 #define CONFIG_SYS_NAND_OOBSIZE 64
285 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
286 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
287 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
288 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
289 48, 49, 50, 51, 52, 53, 54, 55,\
290 56, 57, 58, 59, 60, 61, 62, 63}
291 #define CONFIG_SYS_NAND_ECCSIZE 256
292 #define CONFIG_SYS_NAND_ECCBYTES 3
293 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
294 #define CONFIG_SPL_NAND_SOFTECC
296 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
298 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
304 #if defined(CONFIG_CMD_NET)
305 #define CONFIG_DRIVER_TI_EMAC
306 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
308 #define CONFIG_BOOTP_DNS
309 #define CONFIG_BOOTP_DNS2
310 #define CONFIG_BOOTP_SEND_HOSTNAME
311 #define CONFIG_NET_RETRY_COUNT 10
314 #define CONFIG_SPLASH_SCREEN
315 #define CONFIG_VIDEO_BMP_RLE8
316 #define CONFIG_VIDEO_OMAP3
318 #endif /* __CONFIG_H */