3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5200
33 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
34 #define CONFIG_MCC200 1 /* ... on MCC200 board */
36 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
38 #define CONFIG_MISC_INIT_R
40 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
41 #define BOOTFLAG_WARM 0x02 /* Software reboot */
43 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
44 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
45 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
49 * Serial console configuration
51 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
52 #define CONFIG_BAUDRATE 115200
53 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
57 * 0x40000000 - 0x4fffffff - PCI Memory
58 * 0x50000000 - 0x50ffffff - PCI IO Space
61 #define CONFIG_PCI_PNP 1
62 #define CONFIG_PCI_SCAN_SHOW 1
63 #undef CONFIG_PCI_SCAN_SHOW
65 #define CONFIG_PCI_MEM_BUS 0x40000000
66 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
67 #define CONFIG_PCI_MEM_SIZE 0x10000000
69 #define CONFIG_PCI_IO_BUS 0x50000000
70 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
71 #define CONFIG_PCI_IO_SIZE 0x01000000
73 #define CONFIG_NET_MULTI 1
75 #define CONFIG_EEPRO100 1
76 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
79 #define ADD_PCI_CMD CFG_CMD_PCI
82 #define CONFIG_DOS_PARTITION
86 #define CONFIG_USB_OHCI
87 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
88 #define CONFIG_USB_STORAGE
93 #define ADD_DOC_CMD CFG_CMD_DOC
98 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
111 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
112 #include <cmd_confdefs.h>
117 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
119 #define CONFIG_PREBOOT "echo;" \
120 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
123 #undef CONFIG_BOOTARGS
125 #define CONFIG_EXTRA_ENV_SETTINGS \
127 "hostname=mcc200\0" \
128 "nfsargs=setenv bootargs root=/dev/nfs rw " \
129 "nfsroot=${serverip}:${rootpath}\0" \
130 "ramargs=setenv bootargs root=/dev/ram rw\0" \
131 "addip=setenv bootargs ${bootargs} " \
132 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
133 ":${hostname}:${netdev}:off panic=1\0" \
134 "flash_nfs=run nfsargs addip;" \
135 "bootm ${kernel_addr}\0" \
136 "flash_self=run ramargs addip;" \
137 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
138 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
139 "rootpath=/opt/eldk/ppc_82xx\0" \
140 "bootfile=/tftpboot/mcc200/uImage\0" \
141 "baudrate=115200\0" \
142 "load=tftp 100000 /tftpboot/mcc200/u-boot.bin\0" \
143 "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
144 "cp.b 100000 fff00000 40000;" \
145 "setenv filesize;saveenv\0" \
146 "upd=run load;run update\0" \
147 "serverip=192.168.1.1\0" \
148 "ipaddr=192.168.133.144\0" \
149 "netmask=255.255.0.0\0" \
151 "ethaddr=00:02:44:7d:73:3b\0" \
154 #define CONFIG_BOOTCOMMAND "run flash_self"
157 * IPB Bus clocking configuration.
159 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
164 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
165 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
167 #define CFG_I2C_SPEED 100000 /* 100 kHz */
168 #define CFG_I2C_SLAVE 0x7F
171 * EEPROM configuration
173 #define CFG_I2C_EEPROM_ADDR 0x58
174 #define CFG_I2C_EEPROM_ADDR_LEN 1
175 #define CFG_EEPROM_PAGE_WRITE_BITS 4
176 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
181 #define CONFIG_RTC_PCF8563
182 #define CFG_I2C_RTC_ADDR 0x51
185 * Disk-On-Chip configuration
187 #define CFG_DOC_SHORT_TIMEOUT
188 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
190 #define CFG_DOC_SUPPORT_2000
191 #define CFG_DOC_SUPPORT_MILLENNIUM
192 #define CFG_DOC_BASE 0xE0000000
193 #define CFG_DOC_SIZE 0x00100000
196 * Flash configuration (8,16 or 32 MB)
197 * TEXT base always at 0xFFF00000
198 * ENV_ADDR always at 0xFFF40000
199 * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
200 * 0xFE000000 for 32 MB
201 * 0xFF000000 for 16 MB
202 * 0xFF800000 for 8 MB
204 #define CFG_FLASH_BASE 0xfc000000
205 #define CFG_FLASH_SIZE 0x04000000
207 #define CFG_FLASH_CFI /* The flash is CFI compatible */
208 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
210 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
212 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
213 #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
215 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
216 #define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
218 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
219 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
221 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
222 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
224 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
226 #define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
227 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
228 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
230 /* Address and size of Redundant Environment Sector */
231 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
232 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
234 #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
239 #define CFG_MBAR 0xf0000000
240 #define CFG_SDRAM_BASE 0x00000000
241 #define CFG_DEFAULT_MBAR 0x80000000
243 /* Use SRAM until RAM will be available */
244 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
245 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
248 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
249 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
250 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
252 #define CFG_MONITOR_BASE TEXT_BASE
253 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
254 # define CFG_RAMBOOT 1
257 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
258 #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
259 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
262 * Ethernet configuration
264 #define CONFIG_MPC5xxx_FEC 1
266 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
268 /* #define CONFIG_FEC_10MBIT 1 */
269 #define CONFIG_PHY_ADDR 1
274 //###CHD: MSB = 1 -> 64MB: funktioniert nicht: ERRATA - BUG?
275 //###CHD: 0x10000004 = 32MB SDRAM
276 //###CHD: 0x90000004 = 64MB SDRAM
277 #define CFG_GPS_PORT_CONFIG 0x10000004
280 * Miscellaneous configurable options
282 #define CFG_LONGHELP /* undef to save memory */
283 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
284 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
285 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
287 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
289 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
290 #define CFG_MAXARGS 16 /* max number of command args */
291 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
293 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
294 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
296 #define CFG_LOAD_ADDR 0x100000 /* default load address */
298 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
301 * Various low-level settings
303 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
304 #define CFG_HID0_FINAL HID0_ICE
306 #define CFG_BOOTCS_START CFG_FLASH_BASE
307 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
308 #define CFG_BOOTCS_CFG 0x0004fb00
309 #define CFG_CS0_START CFG_FLASH_BASE
310 #define CFG_CS0_SIZE CFG_FLASH_SIZE
311 #define CFG_CS1_START CFG_DOC_BASE
312 #define CFG_CS1_SIZE CFG_DOC_SIZE
313 #define CFG_CS1_CFG 0x00047800
315 #define CFG_CS_BURST 0x00000000
316 #define CFG_CS_DEADCYCLE 0x33333333
318 #define CFG_RESET_ADDRESS 0xff000000
320 /*-----------------------------------------------------------------------
322 *-----------------------------------------------------------------------
324 #define CONFIG_USB_CLOCK 0x0001BBBB
325 #define CONFIG_USB_CONFIG 0x00005000
327 #endif /* __CONFIG_H */