3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5200
33 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
34 #define CONFIG_MCC200 1 /* ... on MCC200 board */
36 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
38 #define CONFIG_MISC_INIT_R
40 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
41 #define BOOTFLAG_WARM 0x02 /* Software reboot */
43 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
44 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
45 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
49 * Serial console configuration
51 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
52 #define CONFIG_BAUDRATE 115200
53 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
56 //###CHD: MPC5100 gibt es nicht -> weg damit!
57 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
60 * 0x40000000 - 0x4fffffff - PCI Memory
61 * 0x50000000 - 0x50ffffff - PCI IO Space
65 #define CONFIG_PCI_PNP 1
66 #define CONFIG_PCI_SCAN_SHOW 1
67 #undef CONFIG_PCI_SCAN_SHOW
69 #define CONFIG_PCI_MEM_BUS 0x40000000
70 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
71 #define CONFIG_PCI_MEM_SIZE 0x10000000
73 #define CONFIG_PCI_IO_BUS 0x50000000
74 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
75 #define CONFIG_PCI_IO_SIZE 0x01000000
77 #define CONFIG_NET_MULTI 1
79 #define CONFIG_EEPRO100 1
80 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
83 #define ADD_PCI_CMD CFG_CMD_PCI
87 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
92 #define CONFIG_DOS_PARTITION
96 #define CONFIG_USB_OHCI
97 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
98 #define CONFIG_USB_STORAGE
100 #define ADD_USB_CMD 0
103 //###CHD: BOOTROm raus!
104 #if defined(CONFIG_BOOT_ROM)
105 #define ADD_DOC_CMD 0
107 #define ADD_DOC_CMD CFG_CMD_DOC
113 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
127 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
128 #include <cmd_confdefs.h>
133 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
135 #define CONFIG_PREBOOT "echo;" \
136 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
139 #undef CONFIG_BOOTARGS
141 #define CONFIG_EXTRA_ENV_SETTINGS \
144 "nfsargs=setenv bootargs root=/dev/nfs rw " \
145 "nfsroot=${serverip}:${rootpath}\0" \
146 "ramargs=setenv bootargs root=/dev/ram rw\0" \
147 "addip=setenv bootargs ${bootargs} " \
148 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
149 ":${hostname}:${netdev}:off panic=1\0" \
150 "flash_nfs=run nfsargs addip;" \
151 "bootm ${kernel_addr}\0" \
152 "flash_self=run ramargs addip;" \
153 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
154 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
155 "rootpath=/opt/eldk30/ppc_82xx\0" \
156 "bootfile=/tftpboot/LMPC/uImage\0" \
157 "baudrate=115200\0" \
158 "serverip=192.168.0.1\0" \
159 "ipaddr=192.168.0.2\0" \
160 "ethaddr=00:02:44:7d:73:3b\0" \
163 #define CONFIG_BOOTCOMMAND "run flash_self"
165 #if defined(CONFIG_MPC5200)
167 * IPB Bus clocking configuration.
169 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
172 //###CHD: EEProm config RTC config sollte raus, gibt es nciht bei uns auf I2C!
176 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
177 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
179 #define CFG_I2C_SPEED 100000 /* 100 kHz */
180 #define CFG_I2C_SLAVE 0x7F
183 * EEPROM configuration
185 #define CFG_I2C_EEPROM_ADDR 0x58
186 #define CFG_I2C_EEPROM_ADDR_LEN 1
187 #define CFG_EEPROM_PAGE_WRITE_BITS 4
188 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
193 #define CONFIG_RTC_PCF8563
194 #define CFG_I2C_RTC_ADDR 0x51
196 //###CHD: meiner Ansicht nach auch raus!
198 * Disk-On-Chip configuration
201 #define CFG_DOC_SHORT_TIMEOUT
202 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
204 #define CFG_DOC_SUPPORT_2000
205 #define CFG_DOC_SUPPORT_MILLENNIUM
206 #define CFG_DOC_BASE 0xE0000000
207 #define CFG_DOC_SIZE 0x00100000
209 //###CHD: BOOTROm raus!
210 #if defined(CONFIG_BOOT_ROM)
212 * Flash configuration (8,16 or 32 MB)
213 * TEXT base always at 0xFFF00000
214 * ENV_ADDR always at 0xFFF40000
215 * FLASH_BASE at 0xFC000000 for 32 MB
216 * 0xFD000000 for 16 MB
217 * 0xFD800000 for 8 MB
219 #define CFG_FLASH_BASE 0xfc000000
220 #define CFG_FLASH_SIZE 0x02000000
221 #define CFG_BOOTROM_BASE 0xFFF00000
222 #define CFG_BOOTROM_SIZE 0x00080000
223 #define CFG_ENV_ADDR (0xFDF00000 + 0x40000)
226 * Flash configuration (8,16 or 32 MB)
227 * TEXT base always at 0xFFF00000
228 * ENV_ADDR always at 0xFFF40000
229 * FLASH_BASE at 0xFE000000 for 32 MB
230 * 0xFF000000 for 16 MB
231 * 0xFF800000 for 8 MB
233 #define CFG_FLASH_BASE 0xfe000000
234 #define CFG_FLASH_SIZE 0x02000000
235 #define CFG_ENV_ADDR (0xFFF00000 + 0x40000)
237 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
239 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
241 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
242 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
243 #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
244 #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
245 #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
247 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
249 #undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
253 * Environment settings
255 #define CFG_ENV_IS_IN_FLASH 1
256 #define CFG_ENV_SIZE 0x10000
257 #define CFG_ENV_SECT_SIZE 0x40000
258 #define CONFIG_ENV_OVERWRITE 1
263 #define CFG_MBAR 0xf0000000
264 #define CFG_SDRAM_BASE 0x00000000
265 #define CFG_DEFAULT_MBAR 0x80000000
267 /* Use SRAM until RAM will be available */
268 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
269 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
272 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
273 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
274 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
276 #define CFG_MONITOR_BASE TEXT_BASE
277 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
278 # define CFG_RAMBOOT 1
281 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
282 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
283 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
286 * Ethernet configuration
288 #define CONFIG_MPC5xxx_FEC 1
290 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
292 /* #define CONFIG_FEC_10MBIT 1 */
293 #define CONFIG_PHY_ADDR 0x00
298 //###CHD: MSB = 1 -> 64MB: funktioniert nicht: ERRATA - BUG?
299 //###CHD: 0x10000004 = 32MB SDRAM
300 //###CHD: 0x90000004 = 64MB SDRAM
301 #define CFG_GPS_PORT_CONFIG 0x10000004
304 * Miscellaneous configurable options
306 #define CFG_LONGHELP /* undef to save memory */
307 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
308 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
309 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
311 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
313 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
314 #define CFG_MAXARGS 16 /* max number of command args */
315 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
317 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
318 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
320 #define CFG_LOAD_ADDR 0x100000 /* default load address */
322 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
325 * Various low-level settings
327 #if defined(CONFIG_MPC5200)
328 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
329 #define CFG_HID0_FINAL HID0_ICE
331 #define CFG_HID0_INIT 0
332 #define CFG_HID0_FINAL 0
335 //###CHD: hier sollte das BOOT_ROM raus!
336 #if defined(CONFIG_BOOT_ROM)
337 #define CFG_BOOTCS_START CFG_BOOTROM_BASE
338 #define CFG_BOOTCS_SIZE CFG_BOOTROM_SIZE
339 #define CFG_BOOTCS_CFG 0x00047800
340 #define CFG_CS0_START CFG_BOOTROM_BASE
341 #define CFG_CS0_SIZE CFG_BOOTROM_SIZE
342 #define CFG_CS1_START CFG_FLASH_BASE
343 #define CFG_CS1_SIZE CFG_FLASH_SIZE
344 #define CFG_CS1_CFG 0x0004fb00
346 #define CFG_BOOTCS_START CFG_FLASH_BASE
347 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
348 #define CFG_BOOTCS_CFG 0x0004fb00
349 #define CFG_CS0_START CFG_FLASH_BASE
350 #define CFG_CS0_SIZE CFG_FLASH_SIZE
351 #define CFG_CS1_START CFG_DOC_BASE
352 #define CFG_CS1_SIZE CFG_DOC_SIZE
353 #define CFG_CS1_CFG 0x00047800
356 #define CFG_CS_BURST 0x00000000
357 #define CFG_CS_DEADCYCLE 0x33333333
359 #define CFG_RESET_ADDRESS 0xff000000
361 /*-----------------------------------------------------------------------
363 *-----------------------------------------------------------------------
365 #define CONFIG_USB_CLOCK 0x0001BBBB
366 #define CONFIG_USB_CONFIG 0x00005000
368 /*-----------------------------------------------------------------------
369 * IDE/ATA stuff Supports IDE harddisk
370 *-----------------------------------------------------------------------
373 //###CHD: eigentlich das ganze IDE zeugs raus (IDE wird derzeit nciht mehr gescannt!)
374 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
376 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
377 #undef CONFIG_IDE_LED /* LED for ide not supported */
379 #undef CONFIG_IDE_RESET /* reset for ide supported */
380 #define CONFIG_IDE_PREINIT
381 #undef CONFIG_IDE_PREINIT
383 #define CFG_IDE_MAXBUS 0 /* max. 1 IDE bus */
384 #define CFG_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
386 #define CFG_ATA_IDE0_OFFSET 0x0000
388 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
390 /* Offset for data I/O */
391 #define CFG_ATA_DATA_OFFSET (0x0060)
393 /* Offset for normal register accesses */
394 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
396 /* Offset for alternate registers */
397 #define CFG_ATA_ALT_OFFSET (0x005C)
399 /* Interval between registers */
400 #define CFG_ATA_STRIDE 4
402 #endif /* __CONFIG_H */