1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
6 #ifndef _CONFIG_DB_MV7846MP_GP_H
7 #define _CONFIG_DB_MV7846MP_GP_H
9 #include <linux/sizes.h>
12 * High Level Configuration Options (easy to change)
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
22 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
24 /* SPI NOR flash default params, used by sf commands */
26 /* Environment in SPI NOR flash */
28 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
31 * mv-common.h should be defined after CMD configs since it used them
32 * to enable certain macros
34 #include "mv-common.h"
37 * Memory layout while starting into the bin_hdr via the
40 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
41 * 0x4000.4030 bin_hdr start address
42 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
43 * 0x4007.fffc BootROM stack top
45 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
46 * L2 cache thus cannot be used.
52 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
54 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
55 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
57 /* SPL related SPI defines */
59 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
60 #define CONFIG_SYS_SDRAM_SIZE SZ_1G
62 #endif /* _CONFIG_DB_MV7846MP_GP_H */