1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Menlosystems M53Menlo configuration
5 * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
9 #ifndef __M53MENLO_CONFIG_H__
10 #define __M53MENLO_CONFIG_H__
12 #include <asm/arch/imx-regs.h>
14 #define CONFIG_REVISION_TAG
15 #define CONFIG_SYS_FSL_CLK
17 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
20 * Memory configurations
22 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
23 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
24 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
25 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
26 #define PHYS_SDRAM_SIZE (gd->ram_size)
27 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
28 #define CONFIG_SYS_MEMTEST_START 0x70000000
29 #define CONFIG_SYS_MEMTEST_END 0x8ff00000
31 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
32 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
33 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
35 #define CONFIG_SYS_INIT_SP_OFFSET \
36 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
37 #define CONFIG_SYS_INIT_SP_ADDR \
38 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
41 * U-Boot general configurations
43 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
44 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
45 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
46 /* Boot argument buffer size */
51 #define CONFIG_MXC_UART
52 #define CONFIG_MXC_UART_BASE UART1_BASE
58 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
59 #define CONFIG_SYS_FSL_ESDHC_NUM 1
65 #define CONFIG_ENV_SIZE (16 * 1024)
66 #ifdef CONFIG_CMD_NAND
67 #define CONFIG_SYS_MAX_NAND_DEVICE 1
68 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
69 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
70 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
71 #define CONFIG_SYS_NAND_LARGEPAGE
72 #define CONFIG_MXC_NAND_HWECC
74 /* Environment is in NAND */
75 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
76 #define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
77 #define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
78 #define CONFIG_ENV_OFFSET_REDUND \
79 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
83 * Ethernet on SOC (FEC)
86 #define CONFIG_FEC_MXC
87 #define IMX_FEC_BASE FEC_BASE_ADDR
88 #define CONFIG_FEC_MXC_PHYADDR 0x0
90 #define CONFIG_DISCOVER_PHY
91 #define CONFIG_FEC_XCV_TYPE RMII
92 #define CONFIG_ETHPRIME "FEC0"
99 #define CONFIG_SYS_I2C
100 #define CONFIG_SYS_I2C_MXC
101 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
102 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
103 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
104 #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
110 #ifdef CONFIG_CMD_DATE
111 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
112 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
118 #ifdef CONFIG_CMD_USB
119 #define CONFIG_MXC_USB_PORT 1
120 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
121 #define CONFIG_MXC_USB_FLAGS 0
127 #ifdef CONFIG_CMD_SATA
128 #define CONFIG_SYS_SATA_MAX_DEVICE 1
129 #define CONFIG_DWC_AHSATA_PORT_ID 0
130 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
137 #define CONFIG_VIDEO_BMP_RLE8
138 #define CONFIG_VIDEO_BMP_GZIP
139 #define CONFIG_SPLASH_SCREEN
140 #define CONFIG_SPLASHIMAGE_GUARD
141 #define CONFIG_SPLASH_SCREEN_ALIGN
142 #define CONFIG_BMP_16BPP
143 #define CONFIG_VIDEO_LOGO
144 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
147 #define CONFIG_SYS_LDB_CLOCK 33260000
148 #define CONFIG_IMX_VIDEO_SKIP
149 #define CONFIG_SPLASH_SOURCE
152 #define CONFIG_FSL_IIM
159 #define CONFIG_CMDLINE_TAG
160 #define CONFIG_INITRD_TAG
161 #define CONFIG_REVISION_TAG
162 #define CONFIG_SETUP_MEMORY_TAGS
163 #define CONFIG_BOOTFILE "boot/fitImage"
164 #define CONFIG_LOADADDR 0x70800000
165 #define CONFIG_BOOTCOMMAND "run mmc_mmc"
166 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
171 #define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
172 #define CONFIG_SPL_PAD_TO 0x8000
173 #define CONFIG_SPL_STACK 0x70004000
175 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
176 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
177 #define CONFIG_SYS_NAND_OOBSIZE 64
178 #define CONFIG_SYS_NAND_PAGE_COUNT 64
179 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
180 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
185 #define CONFIG_HOSTNAME "m53menlo"
187 #define CONFIG_EXTRA_ENV_SETTINGS \
188 "consdev=ttymxc0\0" \
189 "baudrate=115200\0" \
190 "bootscript=boot.scr\0" \
194 "kernel_addr_r=0x72000000\0" \
195 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
196 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
198 "splashsource=mmc_fs\0" \
199 "splashfile=boot/usplash.bmp.gz\0" \
200 "splashimage=0x88000000\0" \
202 "stdout=serial,vidconsole\0" \
203 "stderr=serial,vidconsole\0" \
205 "setenv bootargs ${bootargs} " \
206 "console=${consdev},${baudrate}\0" \
208 "setenv bootargs ${bootargs} " \
209 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
210 ":${hostname}:${netdev}:off\0" \
211 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
213 "setenv bootargs ${bootargs} ${miscargs}\0" \
214 "addargs=run addcons addmisc addmtd\0" \
216 "mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \
217 "${kernel_addr_r} ${bootfile}\0" \
218 "miscargs=nohlt panic=1\0" \
219 "mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
222 "run mmcload mmcargs addargs ; " \
223 "bootm ${kernel_addr_r}\0" \
224 "netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
226 "run netload nfsargs addip addargs ; " \
227 "bootm ${kernel_addr_r}\0" \
229 "setenv bootargs root=/dev/nfs rw " \
230 "nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0" \
233 "if test -e mmc 0:1 ${bootscript} ; then " \
234 "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
236 "echo Running bootscript... ; " \
237 "source ${kernel_addr_r} ; " \
241 #if defined(CONFIG_SPL_BUILD)
242 #undef CONFIG_WATCHDOG
243 #define CONFIG_HW_WATCHDOG
246 #endif /* __M53MENLO_CONFIG_H__ */