1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Menlosystems M53Menlo configuration
5 * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
9 #ifndef __M53MENLO_CONFIG_H__
10 #define __M53MENLO_CONFIG_H__
12 #include <asm/arch/imx-regs.h>
15 * Memory configurations
17 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
18 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
19 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
20 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
21 #define PHYS_SDRAM_SIZE (gd->ram_size)
23 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
24 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
25 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
27 #define CONFIG_SYS_INIT_SP_OFFSET \
28 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
29 #define CONFIG_SYS_INIT_SP_ADDR \
30 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
33 * U-Boot general configurations
35 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
36 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
37 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
38 /* Boot argument buffer size */
43 #define CONFIG_MXC_UART_BASE UART1_BASE
49 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
50 #define CONFIG_SYS_FSL_ESDHC_NUM 1
56 #ifdef CONFIG_CMD_NAND
57 #define CONFIG_SYS_MAX_NAND_DEVICE 1
58 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
59 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
60 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
61 #define CONFIG_SYS_NAND_LARGEPAGE
62 #define CONFIG_MXC_NAND_HWECC
64 /* Environment is in NAND */
65 #define CONFIG_ENV_RANGE (0x00080000) /* 512 KiB */
69 * Ethernet on SOC (FEC)
72 #define CONFIG_FEC_MXC_PHYADDR 0x0
75 #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
80 #ifdef CONFIG_CMD_DATE
81 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
82 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
89 #define CONFIG_MXC_USB_PORT 1
90 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
91 #define CONFIG_MXC_USB_FLAGS 0
97 #ifdef CONFIG_CMD_SATA
98 #define CONFIG_DWC_AHSATA_PORT_ID 0
99 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
106 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
109 #define CONFIG_SYS_LDB_CLOCK 33260000
110 #define CONFIG_IMX_VIDEO_SKIP
113 #define CONFIG_FSL_IIM
120 #define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
121 #define CONFIG_SPL_PAD_TO 0x8000
122 #define CONFIG_SPL_STACK 0x70004000
124 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
129 #define CONFIG_HOSTNAME "m53menlo"
131 #define CONFIG_EXTRA_ENV_SETTINGS \
132 "consdev=ttymxc0\0" \
133 "baudrate=115200\0" \
134 "bootscript=boot.scr\0" \
138 "kernel_addr_r=0x72000000\0" \
139 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
140 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
142 "splashsource=mmc_fs\0" \
143 "splashfile=boot/usplash.bmp.gz\0" \
144 "splashimage=0x88000000\0" \
147 "if test ${mmcpart} -eq 1 ; then " \
148 "setenv mmcpart 2 ; " \
150 "setenv mmcpart 1 ; " \
153 "stdout=serial,vidconsole\0" \
154 "stderr=serial,vidconsole\0" \
156 "setenv bootargs ${bootargs} " \
157 "console=${consdev},${baudrate}\0" \
159 "setenv bootargs ${bootargs} " \
160 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
161 ":${hostname}:${netdev}:off\0" \
162 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
164 "setenv bootargs ${bootargs} ${miscargs}\0" \
165 "addargs=run addcons addmisc addmtd\0" \
167 "mmc rescan || reset ; load mmc ${mmcdev}:${mmcpart} " \
168 "${kernel_addr_r} ${bootfile} || reset\0" \
169 "miscargs=nohlt panic=1\0" \
170 "mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
173 "run mmcload mmcargs addargs || reset ; " \
174 "bootm ${kernel_addr_r} ; reset\0" \
175 "netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
177 "run netload nfsargs addip addargs ; " \
178 "bootm ${kernel_addr_r}\0" \
180 "setenv bootargs root=/dev/nfs rw " \
181 "nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0" \
184 "if test -e mmc 0:1 ${bootscript} ; then " \
185 "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
187 "echo Running bootscript... ; " \
188 "source ${kernel_addr_r} ; " \
192 #endif /* __M53MENLO_CONFIG_H__ */