2 * Aries M53 configuration
3 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __M53EVK_CONFIG_H__
9 #define __M53EVK_CONFIG_H__
11 #define CONFIG_MXC_GPIO
13 #include <asm/arch/imx-regs.h>
15 #define CONFIG_REVISION_TAG
16 #define CONFIG_SYS_FSL_CLK
18 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
23 #define CONFIG_FAT_WRITE
25 #define CONFIG_CMD_BMP
26 #define CONFIG_CMD_DATE
27 #define CONFIG_CMD_NAND
28 #define CONFIG_CMD_NAND_TRIMFFS
29 #define CONFIG_CMD_SATA
32 * Memory configurations
34 #define CONFIG_NR_DRAM_BANKS 2
35 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
36 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
37 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
38 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
39 #define PHYS_SDRAM_SIZE (gd->ram_size)
40 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
41 #define CONFIG_SYS_MEMTEST_START 0x70000000
42 #define CONFIG_SYS_MEMTEST_END 0x8ff00000
44 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
45 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
46 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
48 #define CONFIG_SYS_INIT_SP_OFFSET \
49 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
50 #define CONFIG_SYS_INIT_SP_ADDR \
51 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
53 #define CONFIG_SYS_TEXT_BASE 0x71000000
56 * U-Boot general configurations
58 #define CONFIG_SYS_LONGHELP
59 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
60 #define CONFIG_SYS_PBSIZE \
61 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
62 /* Print buffer size */
63 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
64 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
65 /* Boot argument buffer size */
66 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
67 #define CONFIG_CMDLINE_EDITING /* Command history etc */
72 #define CONFIG_MXC_UART
73 #define CONFIG_MXC_UART_BASE UART2_BASE
74 #define CONFIG_CONS_INDEX 1
80 #define CONFIG_FSL_ESDHC
81 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
82 #define CONFIG_SYS_FSL_ESDHC_NUM 1
88 #define CONFIG_ENV_SIZE (16 * 1024)
89 #ifdef CONFIG_CMD_NAND
90 #define CONFIG_SYS_MAX_NAND_DEVICE 1
91 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
92 #define CONFIG_NAND_MXC
93 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
94 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
95 #define CONFIG_SYS_NAND_LARGEPAGE
96 #define CONFIG_MXC_NAND_HWECC
97 #define CONFIG_SYS_NAND_USE_FLASH_BBT
99 /* Environment is in NAND */
100 #define CONFIG_ENV_IS_IN_NAND
101 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
102 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
103 #define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
104 #define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
105 #define CONFIG_ENV_OFFSET_REDUND \
106 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
108 #define CONFIG_CMD_UBIFS
109 #define CONFIG_CMD_MTDPARTS
110 #define CONFIG_RBTREE
112 #define CONFIG_MTD_DEVICE
113 #define CONFIG_MTD_PARTITIONS
114 #define MTDIDS_DEFAULT "nand0=mxc_nand"
115 #define MTDPARTS_DEFAULT \
116 "mtdparts=mxc_nand:" \
124 #define CONFIG_ENV_IS_NOWHERE
128 * Ethernet on SOC (FEC)
130 #ifdef CONFIG_CMD_NET
131 #define CONFIG_FEC_MXC
132 #define IMX_FEC_BASE FEC_BASE_ADDR
133 #define CONFIG_FEC_MXC_PHYADDR 0x0
135 #define CONFIG_DISCOVER_PHY
136 #define CONFIG_FEC_XCV_TYPE RMII
137 #define CONFIG_PHYLIB
138 #define CONFIG_PHY_MICREL
139 #define CONFIG_ETHPRIME "FEC0"
145 #ifdef CONFIG_CMD_I2C
146 #define CONFIG_SYS_I2C
147 #define CONFIG_SYS_I2C_MXC
148 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
149 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
150 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
151 #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
157 #ifdef CONFIG_CMD_DATE
158 #define CONFIG_RTC_M41T62
159 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
160 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
166 #ifdef CONFIG_CMD_USB
167 #define CONFIG_USB_EHCI
168 #define CONFIG_USB_EHCI_MX5
169 #define CONFIG_USB_HOST_ETHER
170 #define CONFIG_USB_ETHER_ASIX
171 #define CONFIG_USB_ETHER_MCS7830
172 #define CONFIG_USB_ETHER_SMSC95XX
173 #define CONFIG_MXC_USB_PORT 1
174 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
175 #define CONFIG_MXC_USB_FLAGS 0
181 #ifdef CONFIG_CMD_SATA
182 #define CONFIG_DWC_AHSATA
183 #define CONFIG_SYS_SATA_MAX_DEVICE 1
184 #define CONFIG_DWC_AHSATA_PORT_ID 0
185 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
187 #define CONFIG_LIBATA
194 #define CONFIG_VIDEO_IPUV3
195 #define CONFIG_VIDEO_BMP_RLE8
196 #define CONFIG_VIDEO_BMP_GZIP
197 #define CONFIG_SPLASH_SCREEN
198 #define CONFIG_SPLASHIMAGE_GUARD
199 #define CONFIG_SPLASH_SCREEN_ALIGN
200 #define CONFIG_BMP_16BPP
201 #define CONFIG_VIDEO_LOGO
202 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
203 #define CONFIG_IPUV3_CLK 200000000
209 #define CONFIG_CMDLINE_TAG
210 #define CONFIG_INITRD_TAG
211 #define CONFIG_REVISION_TAG
212 #define CONFIG_SETUP_MEMORY_TAGS
213 #define CONFIG_BOOTFILE "fitImage"
214 #define CONFIG_BOOTARGS "console=ttymxc1,115200"
215 #define CONFIG_LOADADDR 0x70800000
216 #define CONFIG_BOOTCOMMAND "run mmc_mmc"
217 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
222 #define CONFIG_SPL_FRAMEWORK
223 #define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
224 #define CONFIG_SPL_BOARD_INIT
225 #define CONFIG_SPL_TEXT_BASE 0x70008000
226 #define CONFIG_SPL_PAD_TO 0x8000
227 #define CONFIG_SPL_STACK 0x70004000
229 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
230 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
231 #define CONFIG_SYS_NAND_OOBSIZE 64
232 #define CONFIG_SYS_NAND_PAGE_COUNT 64
233 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
234 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
239 #define CONFIG_PREBOOT "run try_bootscript"
240 #define CONFIG_HOSTNAME m53evk
242 #define CONFIG_EXTRA_ENV_SETTINGS \
243 "consdev=ttymxc1\0" \
244 "baudrate=115200\0" \
245 "bootscript=boot.scr\0" \
246 "bootdev=/dev/mmcblk0p1\0" \
247 "rootdev=/dev/mmcblk0p2\0" \
249 "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0" \
250 "kernel_addr_r=0x72000000\0" \
252 "setenv bootargs ${bootargs} " \
253 "console=${consdev},${baudrate}\0" \
255 "setenv bootargs ${bootargs} " \
256 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
257 "${netmask}:${hostname}:${netdev}:off\0" \
259 "setenv bootargs ${bootargs} ${miscargs}\0" \
261 "if test \"x${mtdparts}\" == \"x\" ; then " \
262 "mtdparts default ; " \
265 "run adddfltmtd ; " \
266 "setenv bootargs ${bootargs} ${mtdparts}\0" \
267 "addargs=run addcons addmtd addmisc\0" \
270 "load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \
272 "ubi part UBI ; ubifsmount ubi0:rootfs ; " \
273 "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
275 "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
276 "miscargs=nohlt panic=1\0" \
277 "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
279 "setenv bootargs ubi.mtd=5 " \
280 "root=ubi0:rootfs rootfstype=ubifs\0" \
282 "setenv bootargs root=/dev/nfs rw " \
283 "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
285 "run mmcload mmcargs addargs ; " \
286 "bootm ${kernel_addr_r}\0" \
288 "run mmcload ubiargs addargs ; " \
289 "bootm ${kernel_addr_r}\0" \
291 "run mmcload nfsargs addip addargs ; " \
292 "bootm ${kernel_addr_r}\0" \
294 "run ubiload mmcargs addargs ; " \
295 "bootm ${kernel_addr_r}\0" \
297 "run ubiload ubiargs addargs ; " \
298 "bootm ${kernel_addr_r}\0" \
300 "run ubiload nfsargs addip addargs ; " \
301 "bootm ${kernel_addr_r}\0" \
303 "run netload mmcargs addargs ; " \
304 "bootm ${kernel_addr_r}\0" \
306 "run netload ubiargs addargs ; " \
307 "bootm ${kernel_addr_r}\0" \
309 "run netload nfsargs addip addargs ; " \
310 "bootm ${kernel_addr_r}\0" \
313 "if test -e mmc 0:1 ${bootscript} ; then " \
314 "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
316 "echo Running bootscript... ; " \
317 "source ${kernel_addr_r} ; " \
321 #endif /* __M53EVK_CONFIG_H__ */