2 * Aries M53 configuration
3 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __M53EVK_CONFIG_H__
9 #define __M53EVK_CONFIG_H__
11 #define CONFIG_MXC_GPIO
13 #include <asm/arch/imx-regs.h>
15 #define CONFIG_REVISION_TAG
16 #define CONFIG_SYS_FSL_CLK
18 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
21 * Memory configurations
23 #define CONFIG_NR_DRAM_BANKS 2
24 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
25 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
26 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
27 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
28 #define PHYS_SDRAM_SIZE (gd->ram_size)
29 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
30 #define CONFIG_SYS_MEMTEST_START 0x70000000
31 #define CONFIG_SYS_MEMTEST_END 0x8ff00000
33 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
34 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
35 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
37 #define CONFIG_SYS_INIT_SP_OFFSET \
38 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
39 #define CONFIG_SYS_INIT_SP_ADDR \
40 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
42 #define CONFIG_SYS_TEXT_BASE 0x71000000
45 * U-Boot general configurations
47 #define CONFIG_SYS_LONGHELP
48 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
49 #define CONFIG_SYS_PBSIZE \
50 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
51 /* Print buffer size */
52 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
53 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
54 /* Boot argument buffer size */
55 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
56 #define CONFIG_CMDLINE_EDITING /* Command history etc */
61 #define CONFIG_MXC_UART
62 #define CONFIG_MXC_UART_BASE UART2_BASE
63 #define CONFIG_CONS_INDEX 1
69 #define CONFIG_FSL_ESDHC
70 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
71 #define CONFIG_SYS_FSL_ESDHC_NUM 1
77 #define CONFIG_ENV_SIZE (16 * 1024)
78 #ifdef CONFIG_CMD_NAND
79 #define CONFIG_SYS_MAX_NAND_DEVICE 1
80 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
81 #define CONFIG_NAND_MXC
82 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
83 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
84 #define CONFIG_SYS_NAND_LARGEPAGE
85 #define CONFIG_MXC_NAND_HWECC
86 #define CONFIG_SYS_NAND_USE_FLASH_BBT
88 /* Environment is in NAND */
89 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
90 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
91 #define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
92 #define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
93 #define CONFIG_ENV_OFFSET_REDUND \
94 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
96 #define CONFIG_MTD_DEVICE
97 #define CONFIG_MTD_PARTITIONS
98 #define MTDIDS_DEFAULT "nand0=mxc_nand"
99 #define MTDPARTS_DEFAULT \
100 "mtdparts=mxc_nand:" \
110 * Ethernet on SOC (FEC)
112 #ifdef CONFIG_CMD_NET
113 #define CONFIG_FEC_MXC
114 #define IMX_FEC_BASE FEC_BASE_ADDR
115 #define CONFIG_FEC_MXC_PHYADDR 0x0
117 #define CONFIG_DISCOVER_PHY
118 #define CONFIG_FEC_XCV_TYPE RMII
119 #define CONFIG_ETHPRIME "FEC0"
125 #ifdef CONFIG_CMD_I2C
126 #define CONFIG_SYS_I2C
127 #define CONFIG_SYS_I2C_MXC
128 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
129 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
130 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
131 #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
137 #ifdef CONFIG_CMD_DATE
138 #define CONFIG_RTC_M41T62
139 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
140 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
146 #ifdef CONFIG_CMD_USB
147 #define CONFIG_USB_EHCI_MX5
148 #define CONFIG_USB_HOST_ETHER
149 #define CONFIG_USB_ETHER_ASIX
150 #define CONFIG_USB_ETHER_MCS7830
151 #define CONFIG_USB_ETHER_SMSC95XX
152 #define CONFIG_MXC_USB_PORT 1
153 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
154 #define CONFIG_MXC_USB_FLAGS 0
160 #ifdef CONFIG_CMD_SATA
161 #define CONFIG_DWC_AHSATA
162 #define CONFIG_SYS_SATA_MAX_DEVICE 1
163 #define CONFIG_DWC_AHSATA_PORT_ID 0
164 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
166 #define CONFIG_LIBATA
173 #define CONFIG_VIDEO_IPUV3
174 #define CONFIG_VIDEO_BMP_RLE8
175 #define CONFIG_VIDEO_BMP_GZIP
176 #define CONFIG_SPLASH_SCREEN
177 #define CONFIG_SPLASHIMAGE_GUARD
178 #define CONFIG_SPLASH_SCREEN_ALIGN
179 #define CONFIG_BMP_16BPP
180 #define CONFIG_VIDEO_LOGO
181 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
182 #define CONFIG_IPUV3_CLK 200000000
188 #define CONFIG_CMDLINE_TAG
189 #define CONFIG_INITRD_TAG
190 #define CONFIG_REVISION_TAG
191 #define CONFIG_SETUP_MEMORY_TAGS
192 #define CONFIG_BOOTFILE "fitImage"
193 #define CONFIG_BOOTARGS "console=ttymxc1,115200"
194 #define CONFIG_LOADADDR 0x70800000
195 #define CONFIG_BOOTCOMMAND "run mmc_mmc"
196 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
201 #define CONFIG_SPL_FRAMEWORK
202 #define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
203 #define CONFIG_SPL_TEXT_BASE 0x70008000
204 #define CONFIG_SPL_PAD_TO 0x8000
205 #define CONFIG_SPL_STACK 0x70004000
207 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
208 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
209 #define CONFIG_SYS_NAND_OOBSIZE 64
210 #define CONFIG_SYS_NAND_PAGE_COUNT 64
211 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
212 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
217 #define CONFIG_PREBOOT "run try_bootscript"
218 #define CONFIG_HOSTNAME m53evk
220 #define CONFIG_EXTRA_ENV_SETTINGS \
221 "consdev=ttymxc1\0" \
222 "baudrate=115200\0" \
223 "bootscript=boot.scr\0" \
224 "bootdev=/dev/mmcblk0p1\0" \
225 "rootdev=/dev/mmcblk0p2\0" \
227 "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0" \
228 "kernel_addr_r=0x72000000\0" \
230 "setenv bootargs ${bootargs} " \
231 "console=${consdev},${baudrate}\0" \
233 "setenv bootargs ${bootargs} " \
234 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
235 "${netmask}:${hostname}:${netdev}:off\0" \
237 "setenv bootargs ${bootargs} ${miscargs}\0" \
239 "if test \"x${mtdparts}\" == \"x\" ; then " \
240 "mtdparts default ; " \
243 "run adddfltmtd ; " \
244 "setenv bootargs ${bootargs} ${mtdparts}\0" \
245 "addargs=run addcons addmtd addmisc\0" \
248 "load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \
250 "ubi part UBI ; ubifsmount ubi0:rootfs ; " \
251 "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
253 "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
254 "miscargs=nohlt panic=1\0" \
255 "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
257 "setenv bootargs ubi.mtd=5 " \
258 "root=ubi0:rootfs rootfstype=ubifs\0" \
260 "setenv bootargs root=/dev/nfs rw " \
261 "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
263 "run mmcload mmcargs addargs ; " \
264 "bootm ${kernel_addr_r}\0" \
266 "run mmcload ubiargs addargs ; " \
267 "bootm ${kernel_addr_r}\0" \
269 "run mmcload nfsargs addip addargs ; " \
270 "bootm ${kernel_addr_r}\0" \
272 "run ubiload mmcargs addargs ; " \
273 "bootm ${kernel_addr_r}\0" \
275 "run ubiload ubiargs addargs ; " \
276 "bootm ${kernel_addr_r}\0" \
278 "run ubiload nfsargs addip addargs ; " \
279 "bootm ${kernel_addr_r}\0" \
281 "run netload mmcargs addargs ; " \
282 "bootm ${kernel_addr_r}\0" \
284 "run netload ubiargs addargs ; " \
285 "bootm ${kernel_addr_r}\0" \
287 "run netload nfsargs addip addargs ; " \
288 "bootm ${kernel_addr_r}\0" \
291 "if test -e mmc 0:1 ${bootscript} ; then " \
292 "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
294 "echo Running bootscript... ; " \
295 "source ${kernel_addr_r} ; " \
299 #endif /* __M53EVK_CONFIG_H__ */