2 * DENX M53 configuration
3 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __M53EVK_CONFIG_H__
9 #define __M53EVK_CONFIG_H__
12 #define CONFIG_MXC_GPIO
14 #include <asm/arch/imx-regs.h>
16 #define CONFIG_BOARD_EARLY_INIT_F
17 #define CONFIG_REVISION_TAG
18 #define CONFIG_SYS_NO_FLASH
19 #define CONFIG_SYS_FSL_CLK
21 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
26 #define CONFIG_DOS_PARTITION
27 #define CONFIG_FAT_WRITE
29 #define CONFIG_CMD_BMP
30 #define CONFIG_CMD_DATE
31 #define CONFIG_CMD_NAND
32 #define CONFIG_CMD_NAND_TRIMFFS
33 #define CONFIG_CMD_SATA
36 * Memory configurations
38 #define CONFIG_NR_DRAM_BANKS 2
39 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
40 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
41 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
42 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
43 #define PHYS_SDRAM_SIZE (gd->ram_size)
44 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
45 #define CONFIG_SYS_MEMTEST_START 0x70000000
46 #define CONFIG_SYS_MEMTEST_END 0x8ff00000
48 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
49 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
50 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
52 #define CONFIG_SYS_INIT_SP_OFFSET \
53 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
54 #define CONFIG_SYS_INIT_SP_ADDR \
55 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
57 #define CONFIG_SYS_TEXT_BASE 0x71000000
60 * U-Boot general configurations
62 #define CONFIG_SYS_LONGHELP
63 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
64 #define CONFIG_SYS_PBSIZE \
65 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
66 /* Print buffer size */
67 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
68 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
69 /* Boot argument buffer size */
70 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
71 #define CONFIG_CMDLINE_EDITING /* Command history etc */
76 #define CONFIG_MXC_UART
77 #define CONFIG_MXC_UART_BASE UART2_BASE
78 #define CONFIG_CONS_INDEX 1
79 #define CONFIG_BAUDRATE 115200
86 #define CONFIG_GENERIC_MMC
87 #define CONFIG_FSL_ESDHC
88 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
89 #define CONFIG_SYS_FSL_ESDHC_NUM 1
95 #define CONFIG_ENV_SIZE (16 * 1024)
96 #ifdef CONFIG_CMD_NAND
97 #define CONFIG_SYS_MAX_NAND_DEVICE 1
98 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
99 #define CONFIG_NAND_MXC
100 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
101 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
102 #define CONFIG_SYS_NAND_LARGEPAGE
103 #define CONFIG_MXC_NAND_HWECC
104 #define CONFIG_SYS_NAND_USE_FLASH_BBT
106 /* Environment is in NAND */
107 #define CONFIG_ENV_IS_IN_NAND
108 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
109 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
110 #define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
111 #define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
112 #define CONFIG_ENV_OFFSET_REDUND \
113 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
115 #define CONFIG_CMD_UBIFS
116 #define CONFIG_CMD_MTDPARTS
117 #define CONFIG_RBTREE
119 #define CONFIG_MTD_DEVICE
120 #define CONFIG_MTD_PARTITIONS
121 #define MTDIDS_DEFAULT "nand0=mxc_nand"
122 #define MTDPARTS_DEFAULT \
123 "mtdparts=mxc_nand:" \
131 #define CONFIG_ENV_IS_NOWHERE
135 * Ethernet on SOC (FEC)
137 #ifdef CONFIG_CMD_NET
138 #define CONFIG_FEC_MXC
139 #define IMX_FEC_BASE FEC_BASE_ADDR
140 #define CONFIG_FEC_MXC_PHYADDR 0x0
142 #define CONFIG_DISCOVER_PHY
143 #define CONFIG_FEC_XCV_TYPE RMII
144 #define CONFIG_PHYLIB
145 #define CONFIG_PHY_MICREL
146 #define CONFIG_ETHPRIME "FEC0"
152 #ifdef CONFIG_CMD_I2C
153 #define CONFIG_SYS_I2C
154 #define CONFIG_SYS_I2C_MXC
155 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
156 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
157 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
158 #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
164 #ifdef CONFIG_CMD_DATE
165 #define CONFIG_RTC_M41T62
166 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
167 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
173 #ifdef CONFIG_CMD_USB
174 #define CONFIG_USB_EHCI
175 #define CONFIG_USB_EHCI_MX5
176 #define CONFIG_USB_HOST_ETHER
177 #define CONFIG_USB_ETHER_ASIX
178 #define CONFIG_USB_ETHER_MCS7830
179 #define CONFIG_USB_ETHER_SMSC95XX
180 #define CONFIG_MXC_USB_PORT 1
181 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
182 #define CONFIG_MXC_USB_FLAGS 0
188 #ifdef CONFIG_CMD_SATA
189 #define CONFIG_DWC_AHSATA
190 #define CONFIG_SYS_SATA_MAX_DEVICE 1
191 #define CONFIG_DWC_AHSATA_PORT_ID 0
192 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
194 #define CONFIG_LIBATA
201 #define CONFIG_VIDEO_IPUV3
202 #define CONFIG_VGA_AS_SINGLE_DEVICE
203 #define CONFIG_VIDEO_BMP_RLE8
204 #define CONFIG_VIDEO_BMP_GZIP
205 #define CONFIG_SPLASH_SCREEN
206 #define CONFIG_SPLASHIMAGE_GUARD
207 #define CONFIG_SPLASH_SCREEN_ALIGN
208 #define CONFIG_BMP_16BPP
209 #define CONFIG_VIDEO_LOGO
210 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
211 #define CONFIG_IPUV3_CLK 200000000
217 #define CONFIG_CMDLINE_TAG
218 #define CONFIG_INITRD_TAG
219 #define CONFIG_REVISION_TAG
220 #define CONFIG_SETUP_MEMORY_TAGS
221 #define CONFIG_BOOTFILE "fitImage"
222 #define CONFIG_BOOTARGS "console=ttymxc1,115200"
223 #define CONFIG_LOADADDR 0x70800000
224 #define CONFIG_BOOTCOMMAND "run mmc_mmc"
225 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
230 #define CONFIG_SPL_FRAMEWORK
231 #define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
232 #define CONFIG_SPL_BOARD_INIT
233 #define CONFIG_SPL_TEXT_BASE 0x70008000
234 #define CONFIG_SPL_PAD_TO 0x8000
235 #define CONFIG_SPL_STACK 0x70004000
237 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
238 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
239 #define CONFIG_SYS_NAND_OOBSIZE 64
240 #define CONFIG_SYS_NAND_PAGE_COUNT 64
241 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
242 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
247 #define CONFIG_PREBOOT "run try_bootscript"
248 #define CONFIG_HOSTNAME m53evk
250 #define CONFIG_EXTRA_ENV_SETTINGS \
251 "consdev=ttymxc1\0" \
252 "baudrate=115200\0" \
253 "bootscript=boot.scr\0" \
254 "bootdev=/dev/mmcblk0p1\0" \
255 "rootdev=/dev/mmcblk0p2\0" \
257 "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0" \
258 "kernel_addr_r=0x72000000\0" \
260 "setenv bootargs ${bootargs} " \
261 "console=${consdev},${baudrate}\0" \
263 "setenv bootargs ${bootargs} " \
264 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
265 "${netmask}:${hostname}:${netdev}:off\0" \
267 "setenv bootargs ${bootargs} ${miscargs}\0" \
269 "if test \"x${mtdparts}\" == \"x\" ; then " \
270 "mtdparts default ; " \
273 "run adddfltmtd ; " \
274 "setenv bootargs ${bootargs} ${mtdparts}\0" \
275 "addargs=run addcons addmtd addmisc\0" \
278 "load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \
280 "ubi part UBI ; ubifsmount ubi0:rootfs ; " \
281 "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
283 "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
284 "miscargs=nohlt panic=1\0" \
285 "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
287 "setenv bootargs ubi.mtd=5 " \
288 "root=ubi0:rootfs rootfstype=ubifs\0" \
290 "setenv bootargs root=/dev/nfs rw " \
291 "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
293 "run mmcload mmcargs addargs ; " \
294 "bootm ${kernel_addr_r}\0" \
296 "run mmcload ubiargs addargs ; " \
297 "bootm ${kernel_addr_r}\0" \
299 "run mmcload nfsargs addip addargs ; " \
300 "bootm ${kernel_addr_r}\0" \
302 "run ubiload mmcargs addargs ; " \
303 "bootm ${kernel_addr_r}\0" \
305 "run ubiload ubiargs addargs ; " \
306 "bootm ${kernel_addr_r}\0" \
308 "run ubiload nfsargs addip addargs ; " \
309 "bootm ${kernel_addr_r}\0" \
311 "run netload mmcargs addargs ; " \
312 "bootm ${kernel_addr_r}\0" \
314 "run netload ubiargs addargs ; " \
315 "bootm ${kernel_addr_r}\0" \
317 "run netload nfsargs addip addargs ; " \
318 "bootm ${kernel_addr_r}\0" \
321 "if test -e mmc 0:1 ${bootscript} ; then " \
322 "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
324 "echo Running bootscript... ; " \
325 "source ${kernel_addr_r} ; " \
329 #endif /* __M53EVK_CONFIG_H__ */