2 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
3 * on behalf of DENX Software Engineering GmbH
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/regs-base.h>
28 #define CONFIG_MX28 /* i.MX28 SoC */
29 #define CONFIG_MXS_GPIO /* GPIO control */
30 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
33 * Define M28EVK machine type by hand until it lands in mach-types
35 #define MACH_TYPE_M28EVK 3613
37 #define CONFIG_MACH_TYPE MACH_TYPE_M28EVK
39 #define CONFIG_SYS_NO_FLASH
40 #define CONFIG_SYS_ICACHE_OFF
41 #define CONFIG_SYS_DCACHE_OFF
42 #define CONFIG_BOARD_EARLY_INIT_F
43 #define CONFIG_ARCH_CPU_INIT
44 #define CONFIG_ARCH_MISC_INIT
46 #define CONFIG_OF_LIBFDT
52 #define CONFIG_SPL_NO_CPU_SUPPORT_CODE
53 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28"
54 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
55 #define CONFIG_SPL_LIBCOMMON_SUPPORT
56 #define CONFIG_SPL_LIBGENERIC_SUPPORT
61 #include <config_cmd_default.h>
62 #define CONFIG_DISPLAY_CPUINFO
63 #define CONFIG_DOS_PARTITION
65 #define CONFIG_CMD_CACHE
66 #define CONFIG_CMD_DATE
67 #define CONFIG_CMD_DHCP
68 #define CONFIG_CMD_EEPROM
69 #define CONFIG_CMD_EXT2
70 #define CONFIG_CMD_FAT
71 #define CONFIG_CMD_GPIO
72 #define CONFIG_CMD_I2C
73 #define CONFIG_CMD_MII
74 #define CONFIG_CMD_MMC
75 #define CONFIG_CMD_NAND
76 #define CONFIG_CMD_NET
77 #define CONFIG_CMD_NFS
78 #define CONFIG_CMD_PING
79 #define CONFIG_CMD_SETEXPR
81 #define CONFIG_CMD_SPI
82 #define CONFIG_CMD_USB
85 * Memory configurations
87 #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
88 #define PHYS_SDRAM_1 0x40000000 /* Base address */
89 #define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
90 #define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
91 #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
92 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
93 #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
94 #define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
95 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
96 /* Point initial SP in SRAM so SPL can use it too. */
98 #define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
99 #define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
101 #define CONFIG_SYS_INIT_SP_OFFSET \
102 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
103 #define CONFIG_SYS_INIT_SP_ADDR \
104 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
106 * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
107 * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
108 * binary. In case there was more of this mess, 0x100 bytes are skipped.
110 #define CONFIG_SYS_TEXT_BASE 0x40000100
113 * U-Boot general configurations
115 #define CONFIG_SYS_LONGHELP
116 #define CONFIG_SYS_PROMPT "=> "
117 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
118 #define CONFIG_SYS_PBSIZE \
119 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
120 /* Print buffer size */
121 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
122 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
123 /* Boot argument buffer size */
124 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
125 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
126 #define CONFIG_CMDLINE_EDITING /* Command history etc */
127 #define CONFIG_SYS_HUSH_PARSER
128 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
133 #define CONFIG_PL011_SERIAL
134 #define CONFIG_PL011_CLOCK 24000000
135 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
136 #define CONFIG_CONS_INDEX 0
137 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
138 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
143 #ifdef CONFIG_CMD_MMC
145 #define CONFIG_MMC_BOUNCE_BUFFER
146 #define CONFIG_GENERIC_MMC
147 #define CONFIG_MXS_MMC
153 #define CONFIG_APBH_DMA
158 #define CONFIG_ENV_SIZE (16 * 1024)
159 #ifdef CONFIG_CMD_NAND
160 #define CONFIG_NAND_MXS
161 #define CONFIG_SYS_MAX_NAND_DEVICE 1
162 #define CONFIG_SYS_NAND_BASE 0x60000000
163 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
165 /* Environment is in NAND */
166 #define CONFIG_ENV_IS_IN_NAND
167 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
168 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
169 #define CONFIG_ENV_RANGE (512 * 1024)
170 #define CONFIG_ENV_OFFSET 0x300000
171 #define CONFIG_ENV_OFFSET_REDUND \
172 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
174 #define CONFIG_CMD_UBI
175 #define CONFIG_CMD_UBIFS
176 #define CONFIG_CMD_MTDPARTS
177 #define CONFIG_RBTREE
179 #define CONFIG_MTD_DEVICE
180 #define CONFIG_MTD_PARTITIONS
181 #define MTDIDS_DEFAULT "nand0=gpmi-nand.0"
182 #define MTDPARTS_DEFAULT \
183 "mtdparts=gpmi-nand.0:" \
184 "3m(bootloader)ro," \
185 "512k(environment)," \
186 "512k(redundant-environment)," \
190 #define CONFIG_ENV_IS_NOWHERE
194 * Ethernet on SOC (FEC)
196 #ifdef CONFIG_CMD_NET
197 #define CONFIG_ETHPRIME "FEC0"
198 #define CONFIG_FEC_MXC
199 #define CONFIG_FEC_MXC_MULTI
201 #define CONFIG_DISCOVER_PHY
202 #define CONFIG_FEC_XCV_TYPE RMII
208 #ifdef CONFIG_CMD_I2C
209 #define CONFIG_I2C_MXS
210 #define CONFIG_HARD_I2C
211 #define CONFIG_SYS_I2C_SPEED 400000
217 #ifdef CONFIG_CMD_EEPROM
218 #define CONFIG_SYS_I2C_MULTI_EEPROMS
219 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
225 #ifdef CONFIG_CMD_DATE
226 /* Use the internal RTC in the MXS chip */
227 #define CONFIG_RTC_INTERNAL
228 #ifdef CONFIG_RTC_INTERNAL
229 #define CONFIG_RTC_MXS
231 #define CONFIG_RTC_M41T62
232 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
233 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
240 #ifdef CONFIG_CMD_USB
241 #define CONFIG_USB_EHCI
242 #define CONFIG_USB_EHCI_MXS
243 #define CONFIG_EHCI_MXS_PORT 1
244 #define CONFIG_EHCI_IS_TDI
245 #define CONFIG_USB_STORAGE
251 #ifdef CONFIG_CMD_SPI
252 #define CONFIG_HARD_SPI
253 #define CONFIG_MXS_SPI
254 #define CONFIG_SPI_HALF_DUPLEX
255 #define CONFIG_DEFAULT_SPI_BUS 2
256 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
260 #define CONFIG_SPI_FLASH
261 #define CONFIG_SPI_FLASH_STMICRO
262 #define CONFIG_SF_DEFAULT_CS 2
263 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
264 #define CONFIG_SF_DEFAULT_SPEED 24000000
266 #define CONFIG_ENV_SPI_CS 0
267 #define CONFIG_ENV_SPI_BUS 2
268 #define CONFIG_ENV_SPI_MAX_HZ 24000000
269 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
276 #define CONFIG_CMDLINE_TAG
277 #define CONFIG_SETUP_MEMORY_TAGS
278 #define CONFIG_BOOTDELAY 3
279 #define CONFIG_BOOTFILE "uImage"
280 #define CONFIG_BOOTARGS "console=ttyAM0,115200n8 "
281 #define CONFIG_BOOTCOMMAND "run bootcmd_net"
282 #define CONFIG_LOADADDR 0x42000000
283 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
284 #define CONFIG_OF_LIBFDT
289 #define CONFIG_EXTRA_ENV_SETTINGS \
290 "update_nand_full_filename=u-boot.nand\0" \
291 "update_nand_firmware_filename=u-boot.sb\0" \
292 "update_sd_firmware_filename=u-boot.sd\0" \
293 "update_nand_firmware_maxsz=0x100000\0" \
294 "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \
295 "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \
296 "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \
299 "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
300 "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
301 "update_nand_full=" /* Update FCB, DBBT and FW */ \
302 "if tftp ${update_nand_full_filename} ; then " \
303 "run update_nand_get_fcb_size ; " \
304 "nand scrub -y 0x0 ${filesize} ; " \
305 "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \
306 "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
307 "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
308 "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
310 "update_nand_firmware=" /* Update only firmware */ \
311 "if tftp ${update_nand_firmware_filename} ; then " \
312 "run update_nand_get_fcb_size ; " \
313 "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
314 "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \
315 "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
316 "nand erase ${fcb_sz} ${fw_sz} ; " \
317 "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
318 "nand write ${loadaddr} ${fw_off} ${filesize} ; " \
320 "update_sd_firmware=" /* Update the SD firmware partition */ \
321 "if mmc rescan ; then " \
322 "if tftp ${update_sd_firmware_filename} ; then " \
323 "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
324 "setexpr fw_sz ${fw_sz} + 1 ; " \
325 "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
329 #endif /* __M28_H__ */