1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2018-2021 NXP
9 #include <asm/arch/stream_id_lsch3.h>
10 #include <asm/arch/config.h>
11 #include <asm/arch/soc.h>
13 #define CONFIG_REMAKE_ELF
14 #define CONFIG_FSL_LAYERSCAPE
15 #define CONFIG_FSL_TZPC_BP147
16 #define CONFIG_FSL_MEMAC
18 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
19 #define CONFIG_SYS_FLASH_BASE 0x20000000
21 #define CONFIG_SKIP_LOWLEVEL_INIT
24 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
25 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
26 #define CONFIG_VERY_BIG_RAM
27 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
28 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
29 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
30 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
31 #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
32 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
34 #define SPD_EEPROM_ADDRESS1 0x51
35 #define SPD_EEPROM_ADDRESS2 0x52
36 #define SPD_EEPROM_ADDRESS3 0x53
37 #define SPD_EEPROM_ADDRESS4 0x54
38 #define SPD_EEPROM_ADDRESS5 0x55
39 #define SPD_EEPROM_ADDRESS6 0x56
40 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
41 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
42 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
43 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
44 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
45 #define CONFIG_SYS_MONITOR_LEN (936 * 1024)
47 /* Miscellaneous configurable options */
48 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
51 #define CPU_RELEASE_ADDR secondary_boot_addr
53 /* Generic Timer Definitions */
55 * This is not an accurate number. It is used in start.S. The frequency
56 * will be udpated later when get_bus_freq(0) is available.
59 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
61 /* Size of malloc() pool */
62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
65 #define CONFIG_PL01X_SERIAL
66 #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
67 #define CONFIG_SYS_SERIAL0 0x21c0000
68 #define CONFIG_SYS_SERIAL1 0x21d0000
69 #define CONFIG_SYS_SERIAL2 0x21e0000
70 #define CONFIG_SYS_SERIAL3 0x21f0000
71 /*below might needs to be removed*/
72 #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
73 (void *)CONFIG_SYS_SERIAL1, \
74 (void *)CONFIG_SYS_SERIAL2, \
75 (void *)CONFIG_SYS_SERIAL3 }
76 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
79 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
80 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
81 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
82 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
83 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
85 /* Define phy_reset function to boot the MC based on mcinitcmd.
86 * This happens late enough to properly fixup u-boot env MAC addresses.
88 #define CONFIG_RESET_PHY_R
91 * Carve out a DDR region which will not be used by u-boot/Linux
93 * It will be used by MC and Debug Server. The MC region must be
94 * 512MB aligned, so the min size to hide is 512MB.
96 #ifdef CONFIG_FSL_MC_ENET
97 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
100 /* I2C bus multiplexer */
101 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
102 #define I2C_MUX_CH_DEFAULT 0x8
106 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
109 #define CONFIG_SYS_I2C_EEPROM_NXID
110 #define CONFIG_SYS_EEPROM_BUS_NUM 0
113 #define CONFIG_FSL_QIXIS
114 #define CONFIG_QIXIS_I2C_ACCESS
115 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
119 #define CONFIG_SYS_PCI_64BIT
120 #define CONFIG_PCI_SCAN_SHOW
126 #define CONFIG_SCSI_AHCI_PLAT
127 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
128 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
129 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
130 #define CONFIG_SYS_SCSI_MAX_LUN 1
131 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
132 CONFIG_SYS_SCSI_MAX_LUN)
136 #ifdef CONFIG_USB_HOST
137 #ifndef CONFIG_TARGET_LX2162AQDS
138 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
143 #ifdef CONFIG_DM_GPIO
144 #ifndef CONFIG_MPC8XXX_GPIO
145 #define CONFIG_MPC8XXX_GPIO
150 unsigned long get_board_sys_clk(void);
153 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
154 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
156 #define CONFIG_HWCONFIG
157 #define HWCONFIG_BUFFER_SIZE 128
159 /* Monitor Command Prompt */
160 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
161 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
162 sizeof(CONFIG_SYS_PROMPT) + 16)
163 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
164 #define CONFIG_SYS_MAXARGS 64 /* max command args */
166 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
168 /* Initial environment variables */
169 #define XSPI_MC_INIT_CMD \
171 "sf read 0x80640000 0x640000 0x80000 && " \
172 "sf read $fdt_addr_r 0xf00000 0x100000 && " \
173 "env exists secureboot && " \
174 "esbc_validate 0x80640000 && " \
175 "esbc_validate 0x80680000; " \
176 "sf read 0x80a00000 0xa00000 0x300000 && " \
177 "sf read 0x80e00000 0xe00000 0x100000; " \
178 "fsl_mc start mc 0x80a00000 0x80e00000\0"
180 #define SD_MC_INIT_CMD \
181 "mmc read 0x80a00000 0x5000 0x1200;" \
182 "mmc read 0x80e00000 0x7000 0x800;" \
183 "mmc read $fdt_addr_r 0x7800 0x800;" \
184 "env exists secureboot && " \
185 "mmc read 0x80640000 0x3200 0x20 && " \
186 "mmc read 0x80680000 0x3400 0x20 && " \
187 "esbc_validate 0x80640000 && " \
188 "esbc_validate 0x80680000 ;" \
189 "fsl_mc start mc 0x80a00000 0x80e00000\0"
191 #define SD2_MC_INIT_CMD \
192 "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
193 "mmc read 0x80e00000 0x7000 0x800;" \
194 "mmc read $fdt_addr_r 0x7800 0x800;" \
195 "env exists secureboot && " \
196 "mmc read 0x80640000 0x3200 0x20 && " \
197 "mmc read 0x80680000 0x3400 0x20 && " \
198 "esbc_validate 0x80640000 && " \
199 "esbc_validate 0x80680000 ;" \
200 "fsl_mc start mc 0x80a00000 0x80e00000\0"
202 #define EXTRA_ENV_SETTINGS \
203 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
204 "ramdisk_addr=0x800000\0" \
205 "ramdisk_size=0x2000000\0" \
206 "fdt_high=0xa0000000\0" \
207 "initrd_high=0xffffffffffffffff\0" \
208 "fdt_addr=0x64f00000\0" \
209 "kernel_start=0x1000000\0" \
210 "kernelheader_start=0x600000\0" \
211 "scriptaddr=0x80000000\0" \
212 "scripthdraddr=0x80080000\0" \
213 "fdtheader_addr_r=0x80100000\0" \
214 "kernelheader_addr_r=0x80200000\0" \
215 "kernel_addr_r=0x81000000\0" \
216 "kernelheader_size=0x40000\0" \
217 "fdt_addr_r=0x90000000\0" \
218 "load_addr=0xa0000000\0" \
219 "kernel_size=0x2800000\0" \
220 "kernel_addr_sd=0x8000\0" \
221 "kernelhdr_addr_sd=0x3000\0" \
222 "kernel_size_sd=0x14000\0" \
223 "kernelhdr_size_sd=0x20\0" \
224 "console=ttyAMA0,38400n8\0" \
226 "mcmemsize=0x70000000\0" \
228 "scan_dev_for_boot_part=" \
229 "part list ${devtype} ${devnum} devplist; " \
230 "env exists devplist || setenv devplist 1; " \
231 "for distro_bootpart in ${devplist}; do " \
232 "if fstype ${devtype} " \
233 "${devnum}:${distro_bootpart} " \
234 "bootfstype; then " \
235 "run scan_dev_for_boot; " \
239 "load ${devtype} ${devnum}:${distro_bootpart} " \
240 "${scriptaddr} ${prefix}${script}; " \
241 "env exists secureboot && load ${devtype} " \
242 "${devnum}:${distro_bootpart} " \
243 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
244 "&& esbc_validate ${scripthdraddr};" \
245 "source ${scriptaddr}\0"
247 #define XSPI_NOR_BOOTCOMMAND \
249 "sf read 0x806c0000 0x6c0000 0x40000; " \
250 "env exists mcinitcmd && env exists secureboot" \
251 " && esbc_validate 0x806c0000; " \
252 "sf read 0x80d00000 0xd00000 0x100000; " \
253 "env exists mcinitcmd && " \
254 "fsl_mc lazyapply dpl 0x80d00000; " \
255 "run distro_bootcmd;run xspi_bootcmd; " \
256 "env exists secureboot && esbc_halt;"
258 #define SD_BOOTCOMMAND \
259 "env exists mcinitcmd && mmcinfo; " \
260 "mmc read 0x80d00000 0x6800 0x800; " \
261 "env exists mcinitcmd && env exists secureboot " \
262 " && mmc read 0x806C0000 0x3600 0x20 " \
263 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
264 "&& fsl_mc lazyapply dpl 0x80d00000;" \
265 "run distro_bootcmd;run sd_bootcmd;" \
266 "env exists secureboot && esbc_halt;"
268 #define SD2_BOOTCOMMAND \
269 "mmc dev 1; env exists mcinitcmd && mmcinfo; " \
270 "mmc read 0x80d00000 0x6800 0x800; " \
271 "env exists mcinitcmd && env exists secureboot " \
272 " && mmc read 0x806C0000 0x3600 0x20 " \
273 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
274 "&& fsl_mc lazyapply dpl 0x80d00000;" \
275 "run distro_bootcmd;run sd2_bootcmd;" \
276 "env exists secureboot && esbc_halt;"
278 #define BOOT_TARGET_DEVICES(func) \
282 func(SCSI, scsi, 0) \
284 #include <config_distro_bootcmd.h>
286 #endif /* __LX2_COMMON_H */