include/configs/lx2160a_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018-2020 NXP
   4  */
   5
   6 #ifndef __LX2_COMMON_H
   7 #define __LX2_COMMON_H
   8
   9 #include <asm/arch/stream_id_lsch3.h>
  10 #include <asm/arch/config.h>
  11 #include <asm/arch/soc.h>
  12
  13 #define CONFIG_REMAKE_ELF
  14 #define CONFIG_FSL_LAYERSCAPE
  15 #define CONFIG_GICV3
  16 #define CONFIG_FSL_TZPC_BP147
  17 #define CONFIG_FSL_MEMAC
  18
  19 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_SYS_FLASH_BASE           0x20000000
  21
  22 #define CONFIG_SKIP_LOWLEVEL_INIT
  23
  24 /* DDR */
  25 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  26 #define CONFIG_SYS_FSL_DDR_INTLV_256B   /* force 256 byte interleaving */
  27 #define CONFIG_VERY_BIG_RAM
  28 #define CONFIG_SYS_DDR_SDRAM_BASE               0x80000000UL
  29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  30 #define CONFIG_SYS_DDR_BLOCK2_BASE              0x2080000000ULL
  31 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       2
  32 #define CONFIG_SYS_SDRAM_SIZE                   0x200000000UL
  33 #define CONFIG_DDR_SPD
  34 #define CONFIG_DDR_ECC
  35 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  36 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  37 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  38 #define SPD_EEPROM_ADDRESS1             0x51
  39 #define SPD_EEPROM_ADDRESS2             0x52
  40 #define SPD_EEPROM_ADDRESS3             0x53
  41 #define SPD_EEPROM_ADDRESS4             0x54
  42 #define SPD_EEPROM_ADDRESS5             0x55
  43 #define SPD_EEPROM_ADDRESS6             0x56
  44 #define SPD_EEPROM_ADDRESS              SPD_EEPROM_ADDRESS1
  45 #define CONFIG_SYS_SPD_BUS_NUM          0       /* SPD on I2C bus 0 */
  46 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  47 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  48 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  49 #define CONFIG_SYS_MONITOR_LEN          (936 * 1024)
  50
  51 /* Miscellaneous configurable options */
  52 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  53
  54 /* SMP Definitinos  */
  55 #define CPU_RELEASE_ADDR                secondary_boot_func
  56
  57 /* Generic Timer Definitions */
  58 /*
  59  * This is not an accurate number. It is used in start.S. The frequency
  60  * will be udpated later when get_bus_freq(0) is available.
  61  */
  62
  63 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  64
  65 /* Size of malloc() pool */
  66 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 2048 * 1024)
  67
  68 /* Serial Port */
  69 #define CONFIG_PL01X_SERIAL
  70 #define CONFIG_PL011_CLOCK              (get_bus_freq(0) / 4)
  71 #define CONFIG_SYS_SERIAL0              0x21c0000
  72 #define CONFIG_SYS_SERIAL1              0x21d0000
  73 #define CONFIG_SYS_SERIAL2              0x21e0000
  74 #define CONFIG_SYS_SERIAL3              0x21f0000
  75 /*below might needs to be removed*/
  76 #define CONFIG_PL01x_PORTS              {(void *)CONFIG_SYS_SERIAL0, \
  77                                         (void *)CONFIG_SYS_SERIAL1, \
  78                                         (void *)CONFIG_SYS_SERIAL2, \
  79                                         (void *)CONFIG_SYS_SERIAL3 }
  80 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  81
  82 /* MC firmware */
  83 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH         0x20000
  84 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET        0x00F00000
  85 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH         0x20000
  86 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET        0x00F20000
  87 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS        5000
  88
  89 /* Define phy_reset function to boot the MC based on mcinitcmd.
  90  * This happens late enough to properly fixup u-boot env MAC addresses.
  91  */
  92 #define CONFIG_RESET_PHY_R
  93
  94 /*
  95  * Carve out a DDR region which will not be used by u-boot/Linux
  96  *
  97  * It will be used by MC and Debug Server. The MC region must be
  98  * 512MB aligned, so the min size to hide is 512MB.
  99  */
 100 #ifdef CONFIG_FSL_MC_ENET
 101 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE    (256UL * 1024 * 1024)
 102 #endif
 103
 104 /* I2C bus multiplexer */
 105 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 106 #define I2C_MUX_CH_DEFAULT              0x8
 107
 108 /* RTC */
 109 #define RTC
 110 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 111
 112 /* EEPROM */
 113 #define CONFIG_ID_EEPROM
 114 #define CONFIG_SYS_I2C_EEPROM_NXID
 115 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 116 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 117 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 118 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 119 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 120
 121 /* Qixis */
 122 #define CONFIG_FSL_QIXIS
 123 #define CONFIG_QIXIS_I2C_ACCESS
 124 #define CONFIG_SYS_I2C_FPGA_ADDR                0x66
 125
 126 /* PCI */
 127 #ifdef CONFIG_PCI
 128 #define CONFIG_SYS_PCI_64BIT
 129 #define CONFIG_PCI_SCAN_SHOW
 130 #endif
 131
 132 /* MMC */
 133 #ifdef CONFIG_MMC
 134 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 135 #endif
 136
 137 /* SATA */
 138
 139 #ifdef CONFIG_SCSI
 140 #define CONFIG_SCSI_AHCI_PLAT
 141 #define CONFIG_SYS_SATA1                AHCI_BASE_ADDR1
 142 #define CONFIG_SYS_SATA2                AHCI_BASE_ADDR2
 143 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     1
 144 #define CONFIG_SYS_SCSI_MAX_LUN         1
 145 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 146                                         CONFIG_SYS_SCSI_MAX_LUN)
 147 #endif
 148
 149 /* USB */
 150 #ifdef CONFIG_USB
 151 #define CONFIG_HAS_FSL_XHCI_USB
 152 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 153 #endif
 154
 155 /* FlexSPI */
 156 #ifdef CONFIG_NXP_FSPI
 157 #define NXP_FSPI_FLASH_SIZE             SZ_64M
 158 #define NXP_FSPI_FLASH_NUM              1
 159 #endif
 160
 161 #ifndef __ASSEMBLY__
 162 unsigned long get_board_sys_clk(void);
 163 unsigned long get_board_ddr_clk(void);
 164 #endif
 165
 166 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
 167 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
 168 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ / 4)
 169
 170 #define CONFIG_HWCONFIG
 171 #define HWCONFIG_BUFFER_SIZE            128
 172
 173 #define CONFIG_SYS_MMC_ENV_DEV          0
 174
 175 /* Allow to overwrite serial and ethaddr */
 176 #define CONFIG_ENV_OVERWRITE
 177
 178 /* Monitor Command Prompt */
 179 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 180 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 181                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 182 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 183 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 184
 185 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 186
 187 /* Initial environment variables */
 188 #define XSPI_MC_INIT_CMD                                \
 189         "sf probe 0:0 && "                              \
 190         "sf read 0x80640000 0x640000 0x80000 && "       \
 191         "env exists secureboot && "                     \
 192         "esbc_validate 0x80640000 && "                  \
 193         "esbc_validate 0x80680000; "                    \
 194         "sf read 0x80a00000 0xa00000 0x300000 && "      \
 195         "sf read 0x80e00000 0xe00000 0x100000; "        \
 196         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 197
 198 #define SD_MC_INIT_CMD                          \
 199         "mmc read 0x80a00000 0x5000 0x1200;"    \
 200         "mmc read 0x80e00000 0x7000 0x800;"     \
 201         "env exists secureboot && "             \
 202         "mmc read 0x80640000 0x3200 0x20 && "   \
 203         "mmc read 0x80680000 0x3400 0x20 && "   \
 204         "esbc_validate 0x80640000 && "          \
 205         "esbc_validate 0x80680000 ;"            \
 206         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 207
 208 #define SD2_MC_INIT_CMD                         \
 209         "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
 210         "mmc read 0x80e00000 0x7000 0x800;"     \
 211         "env exists secureboot && "             \
 212         "mmc read 0x80640000 0x3200 0x20 && "   \
 213         "mmc read 0x80680000 0x3400 0x20 && "   \
 214         "esbc_validate 0x80640000 && "          \
 215         "esbc_validate 0x80680000 ;"            \
 216         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 217
 218 #define EXTRA_ENV_SETTINGS                      \
 219         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 220         "ramdisk_addr=0x800000\0"               \
 221         "ramdisk_size=0x2000000\0"              \
 222         "fdt_high=0xa0000000\0"                 \
 223         "initrd_high=0xffffffffffffffff\0"      \
 224         "fdt_addr=0x64f00000\0"                 \
 225         "kernel_start=0x1000000\0"              \
 226         "kernelheader_start=0x600000\0"         \
 227         "scriptaddr=0x80000000\0"               \
 228         "scripthdraddr=0x80080000\0"            \
 229         "fdtheader_addr_r=0x80100000\0"         \
 230         "kernelheader_addr_r=0x80200000\0"      \
 231         "kernel_addr_r=0x81000000\0"            \
 232         "kernelheader_size=0x40000\0"           \
 233         "fdt_addr_r=0x90000000\0"               \
 234         "load_addr=0xa0000000\0"                \
 235         "kernel_size=0x2800000\0"               \
 236         "kernel_addr_sd=0x8000\0"               \
 237         "kernelhdr_addr_sd=0x3000\0"            \
 238         "kernel_size_sd=0x1d000\0"              \
 239         "kernelhdr_size_sd=0x20\0"              \
 240         "console=ttyAMA0,38400n8\0"             \
 241         BOOTENV                                 \
 242         "mcmemsize=0x70000000\0"                \
 243         XSPI_MC_INIT_CMD                                \
 244         "scan_dev_for_boot_part="               \
 245                 "part list ${devtype} ${devnum} devplist; "     \
 246                 "env exists devplist || setenv devplist 1; "    \
 247                 "for distro_bootpart in ${devplist}; do "       \
 248                         "if fstype ${devtype} "                 \
 249                                 "${devnum}:${distro_bootpart} " \
 250                                 "bootfstype; then "             \
 251                                 "run scan_dev_for_boot; "       \
 252                         "fi; "                                  \
 253                 "done\0"                                        \
 254         "boot_a_script="                                        \
 255                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 256                         "${scriptaddr} ${prefix}${script}; "    \
 257                 "env exists secureboot && load ${devtype} "     \
 258                         "${devnum}:${distro_bootpart} "         \
 259                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 260                         "&& esbc_validate ${scripthdraddr};"    \
 261                 "source ${scriptaddr}\0"
 262
 263 #define XSPI_NOR_BOOTCOMMAND                                            \
 264                         "sf probe 0:0; "                                \
 265                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 266                         "env exists mcinitcmd && env exists secureboot" \
 267                         " && esbc_validate 0x806c0000; "                \
 268                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 269                         "env exists mcinitcmd && "                      \
 270                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 271                         "run distro_bootcmd;run xspi_bootcmd; "         \
 272                         "env exists secureboot && esbc_halt;"
 273
 274 #define SD_BOOTCOMMAND                                          \
 275                 "env exists mcinitcmd && mmcinfo; "             \
 276                 "mmc read 0x80d00000 0x6800 0x800; "            \
 277                 "env exists mcinitcmd && env exists secureboot "        \
 278                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 279                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 280                 "&& fsl_mc lazyapply dpl 0x80d00000;"           \
 281                 "run distro_bootcmd;run sd_bootcmd;"            \
 282                 "env exists secureboot && esbc_halt;"
 283
 284 #define SD2_BOOTCOMMAND                                         \
 285                 "mmc dev 1; env exists mcinitcmd && mmcinfo; "  \
 286                 "mmc read 0x80d00000 0x6800 0x800; "            \
 287                 "env exists mcinitcmd && env exists secureboot "        \
 288                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 289                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 290                 "&& fsl_mc lazyapply dpl 0x80d00000;"           \
 291                 "run distro_bootcmd;run sd2_bootcmd;"           \
 292                 "env exists secureboot && esbc_halt;"
 293
 294 #define BOOT_TARGET_DEVICES(func) \
 295         func(USB, usb, 0) \
 296         func(MMC, mmc, 0) \
 297         func(MMC, mmc, 1) \
 298         func(SCSI, scsi, 0) \
 299         func(DHCP, dhcp, na)
 300 #include <config_distro_bootcmd.h>
 301
 302 #endif /* __LX2_COMMON_H */