3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 /************************************************************************
22 * lwmon5.h - configuration for lwmon5 board
23 ***********************************************************************/
27 /*-----------------------------------------------------------------------
28 * High Level Configuration Options
29 *----------------------------------------------------------------------*/
30 #define CONFIG_LWMON5 1 /* Board is lwmon5 */
31 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
32 #define CONFIG_440 1 /* ... PPC440 family */
33 #define CONFIG_4xx 1 /* ... PPC4xx family */
34 #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
36 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
37 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
38 #define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
40 /*-----------------------------------------------------------------------
41 * Base addresses -- Note these are effective addresses where the
42 * actual resources get mapped (not physical addresses)
43 *----------------------------------------------------------------------*/
44 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
45 #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
47 #define CFG_BOOT_BASE_ADDR 0xf0000000
48 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
49 #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */
50 #define CFG_MONITOR_BASE TEXT_BASE
51 #define CFG_LIME_BASE_0 0xc0000000
52 #define CFG_LIME_BASE_1 0xc1000000
53 #define CFG_LIME_BASE_2 0xc2000000
54 #define CFG_LIME_BASE_3 0xc3000000
55 #define CFG_FPGA_BASE_0 0xc4000000
56 #define CFG_FPGA_BASE_1 0xc4200000
57 #define CFG_OCM_BASE 0xe0010000 /* ocm */
58 #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
59 #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
60 #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
61 #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
62 #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
64 /* Don't change either of these */
65 #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
67 #define CFG_USB2D0_BASE 0xe0000100
68 #define CFG_USB_DEVICE 0xe0000000
69 #define CFG_USB_HOST 0xe0000400
71 /*-----------------------------------------------------------------------
72 * Initial RAM & stack pointer
73 *----------------------------------------------------------------------*/
74 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
75 #define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
76 #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
77 #define CFG_OCM_DATA_ADDR CFG_OCM_BASE
79 #define CFG_INIT_RAM_END (4 << 10)
80 #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
81 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
82 #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
83 #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
85 /*-----------------------------------------------------------------------
87 *----------------------------------------------------------------------*/
88 #undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */
89 #define CONFIG_BAUDRATE 115200
90 #define CONFIG_SERIAL_MULTI 1
91 /* define this if you want console on UART1 */
92 #define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */
94 #define CFG_BAUDRATE_TABLE \
95 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
97 /*-----------------------------------------------------------------------
99 *----------------------------------------------------------------------*/
100 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
102 /*-----------------------------------------------------------------------
104 *----------------------------------------------------------------------*/
105 #define CFG_FLASH_CFI /* The flash is CFI compatible */
106 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
108 #define CFG_FLASH0 0xFC000000
109 #define CFG_FLASH1 0xF8000000
110 #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
112 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
113 #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
115 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
116 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
118 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
119 #define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
121 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
122 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
124 #define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
125 #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
126 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
128 /* Address and size of Redundant Environment Sector */
129 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
130 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
132 /*-----------------------------------------------------------------------
134 *----------------------------------------------------------------------*/
135 #define CFG_MBYTES_SDRAM (256) /* 256MB */
136 #define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
137 #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
138 #if 0 /* test-only: disable ECC for now */
139 #define CONFIG_DDR_ECC 1 /* enable ECC */
142 #define CONFIG_POST (CFG_POST_ECC)
146 /*-----------------------------------------------------------------------
148 *----------------------------------------------------------------------*/
149 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
150 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
151 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
152 #define CFG_I2C_SLAVE 0x7F
154 #define CFG_I2C_MULTI_EEPROMS
155 #define CFG_I2C_EEPROM_ADDR (0xa8>>1)
156 #define CFG_I2C_EEPROM_ADDR_LEN 1
157 #define CFG_EEPROM_PAGE_WRITE_ENABLE
158 #define CFG_EEPROM_PAGE_WRITE_BITS 3
159 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
161 #define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
162 #define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
164 #define CONFIG_PREBOOT "echo;" \
165 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
168 #undef CONFIG_BOOTARGS
170 #define CONFIG_EXTRA_ENV_SETTINGS \
171 "hostname=lwmon5\0" \
174 "nfsargs=setenv bootargs root=/dev/nfs rw " \
175 "nfsroot=${serverip}:${rootpath}\0" \
176 "ramargs=setenv bootargs root=/dev/ram rw\0" \
177 "addip=setenv bootargs ${bootargs} " \
178 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
179 ":${hostname}:${netdev}:off panic=1\0" \
180 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
181 "flash_nfs=run nfsargs addip addtty;" \
182 "bootm ${kernel_addr}\0" \
183 "flash_self=run ramargs addip addtty;" \
184 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
185 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
187 "rootpath=/opt/eldk/ppc_4xxFP\0" \
188 "bootfile=/tftpboot/lwmon5/uImage\0" \
189 "kernel_addr=FC000000\0" \
190 "ramdisk_addr=FC180000\0" \
191 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
192 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
193 "cp.b 200000 FFF80000 80000\0" \
194 "upd=run load;run update\0" \
195 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
198 #define CONFIG_BOOTCOMMAND "run flash_self"
201 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
203 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
206 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
207 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
209 #define CONFIG_IBM_EMAC4_V4 1
210 #define CONFIG_MII 1 /* MII PHY management */
211 #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
213 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
215 #define CONFIG_HAS_ETH0
216 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
218 #define CONFIG_NET_MULTI 1
219 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
220 #define CONFIG_PHY1_ADDR 1
224 #define CONFIG_USB_OHCI
225 #define CONFIG_USB_STORAGE
227 /* Comment this out to enable USB 1.1 device */
228 #define USB_2_0_DEVICE
230 #define CMD_USB CFG_CMD_USB
232 #define CMD_USB 0 /* no USB on 440GRx */
233 #endif /* CONFIG_440EPX */
236 #define CONFIG_MAC_PARTITION
237 #define CONFIG_DOS_PARTITION
238 #define CONFIG_ISO_PARTITION
240 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
259 #define CONFIG_SUPPORT_VFAT
261 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
262 #include <cmd_confdefs.h>
264 /*-----------------------------------------------------------------------
265 * Miscellaneous configurable options
266 *----------------------------------------------------------------------*/
267 #define CFG_LONGHELP /* undef to save memory */
268 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
269 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
270 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
272 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
274 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
275 #define CFG_MAXARGS 16 /* max number of command args */
276 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
278 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
279 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
281 #define CFG_LOAD_ADDR 0x100000 /* default load address */
282 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
284 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
286 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
287 #define CONFIG_LOOPW 1 /* enable loopw command */
288 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
289 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
290 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
292 /*-----------------------------------------------------------------------
294 *----------------------------------------------------------------------*/
296 #define CONFIG_PCI /* include pci support */
297 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
298 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
299 #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
301 /* Board-specific PCI */
302 #define CFG_PCI_TARGET_INIT
303 #define CFG_PCI_MASTER_INIT
305 #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
306 #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
308 #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
311 * For booting Linux, the board info and command line data
312 * have to be in the first 8 MB of memory, since this is
313 * the maximum mapped by the Linux kernel during initialization.
315 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
317 /*-----------------------------------------------------------------------
318 * External Bus Controller (EBC) Setup
319 *----------------------------------------------------------------------*/
320 #define CFG_FLASH CFG_FLASH_BASE
322 /* Memory Bank 0 (NOR-FLASH) initialization */
323 #define CFG_EBC_PB0AP 0x03050200
324 #define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000)
326 /* Memory Bank 1 (Lime) initialization */
327 #define CFG_EBC_PB1AP 0x01004380
328 #define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000)
330 /* Memory Bank 2 (FPGA) initialization */
331 #define CFG_EBC_PB2AP 0x01004400
332 #define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000)
334 /* Memory Bank 3 (FPGA2) initialization */
335 #define CFG_EBC_PB3AP 0x01004400
336 #define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000)
338 #define CFG_EBC_CFG 0xb8400000
340 /*-----------------------------------------------------------------------
341 * Graphics (Fujitsu Lime)
342 *----------------------------------------------------------------------*/
343 /* SDRAM Clock frequency adjustment register */
344 #define CFG_LIME_SDRAM_CLOCK 0xC1FC0000
345 /* Lime Clock frequency is to set 133MHz */
346 #define CFG_LIME_CLOCK_133MHZ 0x10000
348 /* SDRAM Parameter register */
349 #define CFG_LIME_MMR 0xC1FCFFFC
350 /* SDRAM parameter value */
351 #define CFG_LIME_MMR_VALUE 0x414FB7F2
353 /*-----------------------------------------------------------------------
355 *----------------------------------------------------------------------*/
356 #define CFG_GPIO_PHY1_RST 12
357 #define CFG_GPIO_FLASH_WP 14
358 #define CFG_GPIO_PHY0_RST 22
359 #define CFG_GPIO_WATCHDOG 58
360 #define CFG_GPIO_LIME_S 59
361 #define CFG_GPIO_LIME_RST 60
363 /*-----------------------------------------------------------------------
364 * PPC440 GPIO Configuration
366 #define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
369 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
370 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
371 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
372 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
373 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
374 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
375 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
376 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
377 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
378 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
379 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
380 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
381 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
382 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
383 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
384 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
385 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
386 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
387 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
388 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
389 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
390 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
391 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
392 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
393 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
394 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
395 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
396 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
397 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
398 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
399 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
400 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
404 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
405 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
406 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
407 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
408 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
409 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
410 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
411 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
412 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
413 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
414 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
415 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
416 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
417 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
418 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
419 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
420 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
421 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
422 {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
423 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
424 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
425 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
426 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
427 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
428 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
429 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
430 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \
431 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
432 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
433 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
434 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
435 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
439 /*-----------------------------------------------------------------------
440 * Cache Configuration
441 *----------------------------------------------------------------------*/
442 #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
443 #define CFG_CACHELINE_SIZE 32 /* ... */
444 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
445 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
449 * Internal Definitions
453 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
454 #define BOOTFLAG_WARM 0x02 /* Software reboot */
456 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
457 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
458 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
460 #endif /* __CONFIG_H */