include/configs/lwmon.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /* External logbuffer support */
  32 #define CONFIG_LOGBUFFER
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38
  39 #define CONFIG_MPC823           1       /* This is a MPC823E CPU        */
  40 #define CONFIG_LWMON            1       /* ...on a LWMON board          */
  41
  42 #define CONFIG_SYS_TEXT_BASE    0x40000000
  43
  44 /* Default Ethernet MAC address */
  45 #define CONFIG_ETHADDR          00:11:B0:00:00:00
  46
  47 /* The default Ethernet MAC address can be overwritten just once */
  48 #ifdef CONFIG_ETHADDR
  49 #define CONFIG_OVERWRITE_ETHADDR_ONCE   1
  50 #endif
  51
  52 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f()    */
  53 #define CONFIG_BOARD_POSTCLK_INIT 1     /* Call board_postclk_init()    */
  54 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r()           */
  55
  56 #define CONFIG_LCD              1       /* use LCD controller ...       */
  57 #define CONFIG_HLD1045          1       /* ... with a HLD1045 display   */
  58
  59 #define CONFIG_LCD_LOGO         1       /* print our logo on the LCD    */
  60 #define CONFIG_LCD_INFO         1       /* ... and some board info      */
  61 #define CONFIG_SPLASH_SCREEN            /* ... with splashscreen support*/
  62
  63 #define CONFIG_SERIAL_MULTI     1
  64 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  65 #define CONFIG_8xx_CONS_SCC2    1       /* Console is on SCC2           */
  66
  67 #define CONFIG_BAUDRATE         115200  /* with watchdog >= 38400 needed */
  68
  69 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second      */
  70
  71 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  72
  73 /* pre-boot commands */
  74 #define CONFIG_PREBOOT          "setenv bootdelay 15"
  75
  76 #undef  CONFIG_BOOTARGS
  77
  78 /* POST support */
  79 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE     | \
  80                                  CONFIG_SYS_POST_WATCHDOG | \
  81                                  CONFIG_SYS_POST_RTC       | \
  82                                  CONFIG_SYS_POST_MEMORY   | \
  83                                  CONFIG_SYS_POST_CPU       | \
  84                                  CONFIG_SYS_POST_UART      | \
  85                                  CONFIG_SYS_POST_ETHER    | \
  86                                  CONFIG_SYS_POST_I2C       | \
  87                                  CONFIG_SYS_POST_SPI       | \
  88                                  CONFIG_SYS_POST_USB       | \
  89                                  CONFIG_SYS_POST_SPR       | \
  90                                  CONFIG_SYS_POST_SYSMON)
  91
  92 /*
  93  * Keyboard commands:
  94  * # = 0x28 = ENTER :           enable bootmessages on LCD
  95  * 2 = 0x3A+0x3C = F1 + F3 :    enable update mode
  96  * 3 = 0x3C+0x3F = F3 + F6 :    enable test mode
  97  */
  98
  99 #define CONFIG_BOOTCOMMAND "source 40040000;saveenv"
 100
 101 /*      "gatewayip=10.8.211.250\0"                                      \ */
 102 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 103         "kernel_addr=40080000\0"                                        \
 104         "ramdisk_addr=40280000\0"                                       \
 105         "netmask=255.255.192.0\0"                                       \
 106         "serverip=10.8.2.101\0"                                         \
 107         "ipaddr=10.8.57.0\0"                                            \
 108         "magic_keys=#23\0"                                              \
 109         "key_magic#=28\0"                                               \
 110         "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
 111         "key_magic2=3A+3C\0"                                            \
 112         "key_cmd2=echo *** Entering Update Mode ***;"                   \
 113                 "if fatload ide 0:3 10000 update.scr;"                  \
 114                         "then source 10000;"                            \
 115                         "else echo *** UPDATE FAILED ***;"              \
 116                 "fi\0"                                                  \
 117         "key_magic3=3C+3F\0"                                            \
 118         "key_cmd3=echo *** Entering Test Mode ***;"                     \
 119                 "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
 120         "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
 121         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 122         "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0"     \
 123         "addip=setenv bootargs $bootargs "                              \
 124                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
 125                 "panic=1\0"                                             \
 126         "add_wdt=setenv bootargs $bootargs $wdt_args\0"                 \
 127         "add_misc=setenv bootargs $bootargs runmode\0"                  \
 128         "flash_nfs=run nfsargs addip add_wdt addfb add_misc;"           \
 129                 "bootm $kernel_addr\0"                                  \
 130         "flash_self=run ramargs addip add_wdt addfb add_misc;"          \
 131                 "bootm $kernel_addr $ramdisk_addr\0"                    \
 132         "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;"                   \
 133                 "run nfsargs addip add_wdt addfb;bootm\0"               \
 134         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
 135         "load=tftp 100000 /tftpboot/u-boot.bin\0"                       \
 136         "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
 137         "wdt_args=wdt_8xx=off\0"                                        \
 138         "verify=no"
 139
 140 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 141 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 142
 143 #define CONFIG_WATCHDOG         1       /* watchdog enabled             */
 144 #define CONFIG_SYS_WATCHDOG_FREQ       (CONFIG_SYS_HZ / 20)
 145
 146 #undef  CONFIG_STATUS_LED               /* Status LED disabled          */
 147
 148 /* enable I2C and select the hardware/software driver */
 149 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 150 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 151
 152 #define CONFIG_SYS_I2C_SPEED            93000   /* 93 kHz is supposed to work   */
 153 #define CONFIG_SYS_I2C_SLAVE            0xFE
 154
 155 #ifdef CONFIG_SOFT_I2C
 156 /*
 157  * Software (bit-bang) I2C driver configuration
 158  */
 159 #define PB_SCL          0x00000020      /* PB 26 */
 160 #define PB_SDA          0x00000010      /* PB 27 */
 161
 162 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 163 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 164 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 165 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 166 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 167                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 168 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 169                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 170 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 171 #endif  /* CONFIG_SOFT_I2C */
 172
 173
 174 #define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 175
 176
 177 /*
 178  * Command line configuration.
 179  */
 180 #include <config_cmd_default.h>
 181
 182 #define CONFIG_CMD_ASKENV
 183 #define CONFIG_CMD_BMP
 184 #define CONFIG_CMD_BSP
 185 #define CONFIG_CMD_DATE
 186 #define CONFIG_CMD_DHCP
 187 #define CONFIG_CMD_EEPROM
 188 #define CONFIG_CMD_FAT
 189 #define CONFIG_CMD_I2C
 190 #define CONFIG_CMD_IDE
 191 #define CONFIG_CMD_NFS
 192 #define CONFIG_CMD_SNTP
 193
 194 #ifdef CONFIG_POST
 195 #define CONFIG_CMD_DIAG
 196 #endif
 197
 198
 199 #define CONFIG_MAC_PARTITION
 200 #define CONFIG_DOS_PARTITION
 201
 202 /*
 203  * BOOTP options
 204  */
 205 #define CONFIG_BOOTP_SUBNETMASK
 206 #define CONFIG_BOOTP_GATEWAY
 207 #define CONFIG_BOOTP_HOSTNAME
 208 #define CONFIG_BOOTP_BOOTPATH
 209 #define CONFIG_BOOTP_BOOTFILESIZE
 210
 211
 212 /*
 213  * Miscellaneous configurable options
 214  */
 215 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 216 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 217
 218 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
 219 #ifdef  CONFIG_SYS_HUSH_PARSER
 220 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 221 #endif
 222
 223 #if defined(CONFIG_CMD_KGDB)
 224 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 225 #else
 226 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 227 #endif
 228 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 229 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 230 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 231
 232 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 233 #define CONFIG_SYS_MEMTEST_END          0x00F00000      /* 1 ... 15MB in DRAM   */
 234
 235 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 236
 237 #define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
 238
 239 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 240
 241 /*
 242  * When the watchdog is enabled, output must be fast enough in Linux.
 243  */
 244 #ifdef CONFIG_WATCHDOG
 245 #define CONFIG_SYS_BAUDRATE_TABLE       {               38400, 57600, 115200 }
 246 #else
 247 #define CONFIG_SYS_BAUDRATE_TABLE       {  9600, 19200, 38400, 57600, 115200 }
 248 #endif
 249
 250 /*----------------------------------------------------------------------*/
 251 #define CONFIG_MODEM_SUPPORT    1       /* enable modem initialization stuff */
 252 #undef CONFIG_MODEM_SUPPORT_DEBUG
 253
 254 #define CONFIG_MODEM_KEY_MAGIC  "3C+3D" /* press F3 + F4 keys to enable modem */
 255 #define CONFIG_POST_KEY_MAGIC   "3C+3E" /* press F3 + F5 keys to force POST */
 256 #if 0
 257 #define CONFIG_AUTOBOOT_KEYED           /* Enable "password" protection */
 258 #define CONFIG_AUTOBOOT_PROMPT  \
 259         "\nEnter password - autoboot in %d sec...\n", bootdelay
 260 #define CONFIG_AUTOBOOT_DELAY_STR       "  "    /* "password"   */
 261 #endif
 262 /*----------------------------------------------------------------------*/
 263
 264 /*
 265  * Low Level Configuration Settings
 266  * (address mappings, register initial values, etc.)
 267  * You should know what you are doing if you make changes here.
 268  */
 269 /*-----------------------------------------------------------------------
 270  * Internal Memory Mapped Register
 271  */
 272 #define CONFIG_SYS_IMMR         0xFFF00000
 273
 274 /*-----------------------------------------------------------------------
 275  * Definitions for initial stack pointer and data area (in DPRAM)
 276  */
 277 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 278 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 279 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 280 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 281
 282 /*-----------------------------------------------------------------------
 283  * Start addresses for the final memory configuration
 284  * (Set up by the startup code)
 285  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 286  */
 287 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 288 #define CONFIG_SYS_FLASH_BASE           0x40000000
 289 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
 290 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 291 #else
 292 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 293 #endif
 294 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 295 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 296
 297 /*
 298  * For booting Linux, the board info and command line data
 299  * have to be in the first 8 MB of memory, since this is
 300  * the maximum mapped by the Linux kernel during initialization.
 301  */
 302 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 303 /*-----------------------------------------------------------------------
 304  * FLASH organization
 305  */
 306 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 307 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 308
 309 #define CONFIG_SYS_FLASH_ERASE_TOUT     180000  /* Timeout for Flash Erase (in ms)      */
 310 #define CONFIG_SYS_FLASH_WRITE_TOUT     600     /* Timeout for Flash Write (in ms)      */
 311 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 312 #define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT      2048    /* Timeout for Flash Buffer Write (in ms)       */
 313 /* Buffer size.
 314    We have two flash devices connected in parallel.
 315    Each device incorporates a Write Buffer of 32 bytes.
 316  */
 317 #define CONFIG_SYS_FLASH_BUFFER_SIZE    (2*32)
 318
 319 /* Put environment in flash which is much faster to boot than using the EEPROM  */
 320 #define CONFIG_ENV_IS_IN_FLASH  1
 321 #define CONFIG_ENV_ADDR     0x40040000  /* Address    of Environment Sector     */
 322 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment            */
 323 #define CONFIG_ENV_SECT_SIZE    0x40000 /* we have BIG sectors only :-(         */
 324
 325 /*-----------------------------------------------------------------------
 326  * I2C/EEPROM Configuration
 327  */
 328
 329 #define CONFIG_SYS_I2C_AUDIO_ADDR       0x28    /* Audio volume control                 */
 330 #define CONFIG_SYS_I2C_SYSMON_ADDR      0x2E    /* LM87 System Monitor                  */
 331 #define CONFIG_SYS_I2C_RTC_ADDR 0x51    /* PCF8563 RTC                          */
 332 #define CONFIG_SYS_I2C_POWER_A_ADDR     0x52    /* PCMCIA/USB power switch, channel A   */
 333 #define CONFIG_SYS_I2C_POWER_B_ADDR     0x53    /* PCMCIA/USB power switch, channel B   */
 334 #define CONFIG_SYS_I2C_KEYBD_ADDR       0x56    /* PIC LWE keyboard                     */
 335 #define CONFIG_SYS_I2C_PICIO_ADDR       0x57    /* PIC IO Expander                      */
 336
 337 #undef  CONFIG_USE_FRAM                 /* Use FRAM instead of EEPROM   */
 338
 339 #ifdef CONFIG_USE_FRAM  /* use FRAM */
 340 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x55    /* FRAM FM24CL64                */
 341 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 342 #else                   /* use EEPROM */
 343 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM AT24C164              */
 344 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 345 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* takes up to 10 msec  */
 346 #endif  /* CONFIG_USE_FRAM */
 347 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 348
 349 /* List of I2C addresses to be verified by POST */
 350 #ifdef CONFIG_USE_FRAM
 351 #define CONFIG_SYS_POST_I2C_ADDRS       {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
 352                                          CONFIG_SYS_I2C_SYSMON_ADDR,    \
 353                                          CONFIG_SYS_I2C_RTC_ADDR,       \
 354                                          CONFIG_SYS_I2C_POWER_A_ADDR,   \
 355                                          CONFIG_SYS_I2C_POWER_B_ADDR,   \
 356                                          CONFIG_SYS_I2C_KEYBD_ADDR,     \
 357                                          CONFIG_SYS_I2C_PICIO_ADDR,     \
 358                                          CONFIG_SYS_I2C_EEPROM_ADDR,    \
 359                                         }
 360 #else   /* Use EEPROM - which show up on 8 consequtive addresses */
 361 #define CONFIG_SYS_POST_I2C_ADDRS       {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
 362                                          CONFIG_SYS_I2C_SYSMON_ADDR,    \
 363                                          CONFIG_SYS_I2C_RTC_ADDR,       \
 364                                          CONFIG_SYS_I2C_POWER_A_ADDR,   \
 365                                          CONFIG_SYS_I2C_POWER_B_ADDR,   \
 366                                          CONFIG_SYS_I2C_KEYBD_ADDR,     \
 367                                          CONFIG_SYS_I2C_PICIO_ADDR,     \
 368                                          CONFIG_SYS_I2C_EEPROM_ADDR+0,  \
 369                                          CONFIG_SYS_I2C_EEPROM_ADDR+1,  \
 370                                          CONFIG_SYS_I2C_EEPROM_ADDR+2,  \
 371                                          CONFIG_SYS_I2C_EEPROM_ADDR+3,  \
 372                                          CONFIG_SYS_I2C_EEPROM_ADDR+4,  \
 373                                          CONFIG_SYS_I2C_EEPROM_ADDR+5,  \
 374                                          CONFIG_SYS_I2C_EEPROM_ADDR+6,  \
 375                                          CONFIG_SYS_I2C_EEPROM_ADDR+7,  \
 376                                         }
 377 #endif  /* CONFIG_USE_FRAM */
 378
 379 /*-----------------------------------------------------------------------
 380  * Cache Configuration
 381  */
 382 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 383 #if defined(CONFIG_CMD_KGDB)
 384 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 385 #endif
 386
 387 /*-----------------------------------------------------------------------
 388  * SYPCR - System Protection Control                            11-9
 389  * SYPCR can only be written once after reset!
 390  *-----------------------------------------------------------------------
 391  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 392  */
 393 #if 0 && defined(CONFIG_WATCHDOG)       /* LWMON uses external MAX706TESA WD */
 394 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 395                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 396 #else
 397 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 398 #endif
 399
 400 /*-----------------------------------------------------------------------
 401  * SIUMCR - SIU Module Configuration                            11-6
 402  *-----------------------------------------------------------------------
 403  * PCMCIA config., multi-function pin tri-state
 404  */
 405 /* EARB, DBGC and DBPC are initialised by the HCW */
 406 /* => 0x000000C0 */
 407 #define CONFIG_SYS_SIUMCR       (SIUMCR_GB5E)
 408 /*#define CONFIG_SYS_SIUMCR     (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
 409
 410 /*-----------------------------------------------------------------------
 411  * TBSCR - Time Base Status and Control                         11-26
 412  *-----------------------------------------------------------------------
 413  * Clear Reference Interrupt Status, Timebase freezing enabled
 414  */
 415 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 416
 417 /*-----------------------------------------------------------------------
 418  * PISCR - Periodic Interrupt Status and Control                11-31
 419  *-----------------------------------------------------------------------
 420  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 421  */
 422 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 423
 424 /*-----------------------------------------------------------------------
 425  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 426  *-----------------------------------------------------------------------
 427  * Reset PLL lock status sticky bit, timer expired status bit and timer
 428  * interrupt status bit, set PLL multiplication factor !
 429  */
 430 /* 0x00405000 */
 431 #define CONFIG_SYS_PLPRCR_MF    4       /* (4+1) * 13.2 = 66 MHz Clock */
 432 #define CONFIG_SYS_PLPRCR                                                       \
 433                 (       (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) |             \
 434                         PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |    \
 435                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 436                         PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/   \
 437                 )
 438
 439 #define CONFIG_8xx_GCLK_FREQ    ((CONFIG_SYS_PLPRCR_MF+1)*13200000)
 440
 441 /*-----------------------------------------------------------------------
 442  * SCCR - System Clock and reset Control Register               15-27
 443  *-----------------------------------------------------------------------
 444  * Set clock output, timebase and RTC source and divider,
 445  * power management and some other internal clocks
 446  */
 447 #define SCCR_MASK       SCCR_EBDF11
 448 /* 0x01800000 */
 449 #define CONFIG_SYS_SCCR (SCCR_COM00     | /*SCCR_TBS|*/         \
 450                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 451                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 452                          SCCR_EBDF00 |   SCCR_DFSYNC00 |        \
 453                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 454                          SCCR_DFNH000   |   SCCR_DFLCD100 |     \
 455                          SCCR_DFALCD01)
 456
 457 /*-----------------------------------------------------------------------
 458  * RTCSC - Real-Time Clock Status and Control Register          11-27
 459  *-----------------------------------------------------------------------
 460  */
 461 /* 0x00C3 => 0x0003 */
 462 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 463
 464
 465 /*-----------------------------------------------------------------------
 466  * RCCR - RISC Controller Configuration Register                19-4
 467  *-----------------------------------------------------------------------
 468  */
 469 #define CONFIG_SYS_RCCR 0x0000
 470
 471 /*-----------------------------------------------------------------------
 472  * RMDS - RISC Microcode Development Support Control Register
 473  *-----------------------------------------------------------------------
 474  */
 475 #define CONFIG_SYS_RMDS 0
 476
 477 /*-----------------------------------------------------------------------
 478  *
 479  * Interrupt Levels
 480  *-----------------------------------------------------------------------
 481  */
 482 #define CONFIG_SYS_CPM_INTERRUPT        13      /* SIU_LEVEL6   */
 483
 484 /*-----------------------------------------------------------------------
 485  * PCMCIA stuff
 486  *-----------------------------------------------------------------------
 487  *
 488  */
 489 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0x50000000)
 490 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 491 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0x54000000)
 492 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 493 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0x58000000)
 494 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 495 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0x5C000000)
 496 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 497
 498 /*-----------------------------------------------------------------------
 499  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 500  *-----------------------------------------------------------------------
 501  */
 502
 503 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 504
 505 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 506 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 507 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 508
 509 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 510 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 511
 512 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 513
 514 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 515
 516 /* Offset for data I/O                  */
 517 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 518
 519 /* Offset for normal register accesses  */
 520 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 521
 522 /* Offset for alternate registers       */
 523 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 524
 525 #define CONFIG_SUPPORT_VFAT             /* enable VFAT support */
 526
 527 /*-----------------------------------------------------------------------
 528  *
 529  *-----------------------------------------------------------------------
 530  *
 531  */
 532 #define CONFIG_SYS_DER 0
 533
 534 /*
 535  * Init Memory Controller:
 536  *
 537  * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
 538  */
 539
 540 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 541 #define FLASH_BASE1_PRELIM      0x41000000      /* FLASH bank #1        */
 542
 543 /* used to re-map FLASH:
 544  * restrict access enough to keep SRAM working (if any)
 545  * but not too much to meddle with FLASH accesses
 546  */
 547 #define CONFIG_SYS_REMAP_OR_AM          0xFF000000      /* OR addr mask */
 548 #define CONFIG_SYS_PRELIM_OR_AM 0xFF000000      /* OR addr mask */
 549
 550 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0        */
 551 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_SCY_8_CLK)
 552
 553 #define CONFIG_SYS_OR0_REMAP    ( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 554                                 CONFIG_SYS_OR_TIMING_FLASH)
 555 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
 556                                 CONFIG_SYS_OR_TIMING_FLASH)
 557 /* 16 bit, bank valid */
 558 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 559
 560 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 561 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 562 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 563
 564 /*
 565  * BR3/OR3: SDRAM
 566  *
 567  * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 568  */
 569 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank */
 570 #define SDRAM_PRELIM_OR_AM      0xF0000000      /* map 256 MB (>SDRAM_MAX_SIZE!) */
 571 #define SDRAM_TIMING            OR_SCY_0_CLK    /* SDRAM-Timing */
 572
 573 #define SDRAM_MAX_SIZE          0x08000000      /* max 128 MB SDRAM */
 574
 575 #define CONFIG_SYS_OR3_PRELIM   (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
 576 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 577
 578 /*
 579  * BR5/OR5: Touch Panel
 580  *
 581  * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 582  */
 583 #define TOUCHPNL_BASE           0x20000000
 584 #define TOUCHPNL_OR_AM          0xFFFF8000
 585 #define TOUCHPNL_TIMING         OR_SCY_0_CLK
 586
 587 #define CONFIG_SYS_OR5_PRELIM   (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 588                          TOUCHPNL_TIMING )
 589 #define CONFIG_SYS_BR5_PRELIM   ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
 590
 591 #define CONFIG_SYS_MEMORY_75
 592 #undef  CONFIG_SYS_MEMORY_7E
 593 #undef  CONFIG_SYS_MEMORY_8E
 594
 595 /*
 596  * Memory Periodic Timer Prescaler
 597  */
 598
 599 /* periodic timer for refresh */
 600 #define CONFIG_SYS_MPTPR        0x200
 601
 602 /*
 603  * MAMR settings for SDRAM
 604  */
 605
 606 #define CONFIG_SYS_MAMR_8COL    0x80802114
 607 #define CONFIG_SYS_MAMR_9COL    0x80904114
 608
 609 /*
 610  * MAR setting for SDRAM
 611  */
 612 #define CONFIG_SYS_MAR          0x00000088
 613
 614 #endif  /* __CONFIG_H */