2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
15 /* External logbuffer support */
16 #define CONFIG_LOGBUFFER
19 * High Level Configuration Options
23 #define CONFIG_MPC823 1 /* This is a MPC823E CPU */
24 #define CONFIG_LWMON 1 /* ...on a LWMON board */
26 #define CONFIG_SYS_TEXT_BASE 0x40000000
28 /* Default Ethernet MAC address */
29 #define CONFIG_ETHADDR 00:11:B0:00:00:00
31 /* The default Ethernet MAC address can be overwritten just once */
33 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
36 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
37 #define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init() */
38 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
40 #define CONFIG_LCD 1 /* use LCD controller ... */
41 #define CONFIG_MPC8XX_LCD
42 #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
44 #define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
45 #define CONFIG_LCD_INFO 1 /* ... and some board info */
46 #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
48 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
49 #define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */
51 #define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
53 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
55 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
57 /* pre-boot commands */
58 #define CONFIG_PREBOOT "setenv bootdelay 15"
60 #undef CONFIG_BOOTARGS
63 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
64 CONFIG_SYS_POST_WATCHDOG | \
65 CONFIG_SYS_POST_RTC | \
66 CONFIG_SYS_POST_MEMORY | \
67 CONFIG_SYS_POST_CPU | \
68 CONFIG_SYS_POST_UART | \
69 CONFIG_SYS_POST_ETHER | \
70 CONFIG_SYS_POST_I2C | \
71 CONFIG_SYS_POST_SPI | \
72 CONFIG_SYS_POST_USB | \
73 CONFIG_SYS_POST_SPR | \
74 CONFIG_SYS_POST_SYSMON)
78 * # = 0x28 = ENTER : enable bootmessages on LCD
79 * 2 = 0x3A+0x3C = F1 + F3 : enable update mode
80 * 3 = 0x3C+0x3F = F3 + F6 : enable test mode
83 #define CONFIG_BOOTCOMMAND "source 40040000;saveenv"
85 /* "gatewayip=10.8.211.250\0" \ */
86 #define CONFIG_EXTRA_ENV_SETTINGS \
87 "kernel_addr=40080000\0" \
88 "ramdisk_addr=40280000\0" \
89 "netmask=255.255.192.0\0" \
90 "serverip=10.8.2.101\0" \
91 "ipaddr=10.8.57.0\0" \
94 "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
95 "key_magic2=3A+3C\0" \
96 "key_cmd2=echo *** Entering Update Mode ***;" \
97 "if fatload ide 0:3 10000 update.scr;" \
98 "then source 10000;" \
99 "else echo *** UPDATE FAILED ***;" \
101 "key_magic3=3C+3F\0" \
102 "key_cmd3=echo *** Entering Test Mode ***;" \
103 "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
104 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
105 "ramargs=setenv bootargs root=/dev/ram rw\0" \
106 "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \
107 "addip=setenv bootargs $bootargs " \
108 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
110 "add_wdt=setenv bootargs $bootargs $wdt_args\0" \
111 "add_misc=setenv bootargs $bootargs runmode\0" \
112 "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \
113 "bootm $kernel_addr\0" \
114 "flash_self=run ramargs addip add_wdt addfb add_misc;" \
115 "bootm $kernel_addr $ramdisk_addr\0" \
116 "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \
117 "run nfsargs addip add_wdt addfb;bootm\0" \
118 "rootpath=/opt/eldk/ppc_8xx\0" \
119 "load=tftp 100000 /tftpboot/u-boot.bin\0" \
120 "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
121 "wdt_args=wdt_8xx=off\0" \
124 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
125 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
127 #define CONFIG_WATCHDOG 1 /* watchdog enabled */
128 #define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 20)
130 #undef CONFIG_STATUS_LED /* Status LED disabled */
132 /* enable I2C and select the hardware/software driver */
133 #undef CONFIG_HARD_I2C /* I2C with hardware support */
134 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
136 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
137 #define CONFIG_SYS_I2C_SLAVE 0xFE
139 #ifdef CONFIG_SOFT_I2C
141 * Software (bit-bang) I2C driver configuration
143 #define PB_SCL 0x00000020 /* PB 26 */
144 #define PB_SDA 0x00000010 /* PB 27 */
146 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
147 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
148 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
149 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
150 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
151 else immr->im_cpm.cp_pbdat &= ~PB_SDA
152 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
153 else immr->im_cpm.cp_pbdat &= ~PB_SCL
154 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
155 #endif /* CONFIG_SOFT_I2C */
158 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
162 * Command line configuration.
164 #include <config_cmd_default.h>
166 #define CONFIG_CMD_ASKENV
167 #define CONFIG_CMD_BMP
168 #define CONFIG_CMD_BSP
169 #define CONFIG_CMD_DATE
170 #define CONFIG_CMD_DHCP
171 #define CONFIG_CMD_EEPROM
172 #define CONFIG_CMD_FAT
173 #define CONFIG_CMD_I2C
174 #define CONFIG_CMD_IDE
175 #define CONFIG_CMD_NFS
176 #define CONFIG_CMD_SNTP
179 #define CONFIG_CMD_DIAG
183 #define CONFIG_MAC_PARTITION
184 #define CONFIG_DOS_PARTITION
189 #define CONFIG_BOOTP_SUBNETMASK
190 #define CONFIG_BOOTP_GATEWAY
191 #define CONFIG_BOOTP_HOSTNAME
192 #define CONFIG_BOOTP_BOOTPATH
193 #define CONFIG_BOOTP_BOOTFILESIZE
197 * Miscellaneous configurable options
199 #define CONFIG_SYS_LONGHELP /* undef to save memory */
200 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
202 #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
204 #if defined(CONFIG_CMD_KGDB)
205 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
207 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
209 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
210 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
211 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
213 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
214 #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
216 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
218 #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
220 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
223 * When the watchdog is enabled, output must be fast enough in Linux.
225 #ifdef CONFIG_WATCHDOG
226 #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 57600, 115200 }
229 /*----------------------------------------------------------------------*/
230 #define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */
231 #undef CONFIG_MODEM_SUPPORT_DEBUG
233 #define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */
234 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
236 #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
237 #define CONFIG_AUTOBOOT_PROMPT \
238 "\nEnter password - autoboot in %d sec...\n", bootdelay
239 #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
241 /*----------------------------------------------------------------------*/
244 * Low Level Configuration Settings
245 * (address mappings, register initial values, etc.)
246 * You should know what you are doing if you make changes here.
248 /*-----------------------------------------------------------------------
249 * Internal Memory Mapped Register
251 #define CONFIG_SYS_IMMR 0xFFF00000
253 /*-----------------------------------------------------------------------
254 * Definitions for initial stack pointer and data area (in DPRAM)
256 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
257 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
258 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
259 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
261 /*-----------------------------------------------------------------------
262 * Start addresses for the final memory configuration
263 * (Set up by the startup code)
264 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
266 #define CONFIG_SYS_SDRAM_BASE 0x00000000
267 #define CONFIG_SYS_FLASH_BASE 0x40000000
268 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
269 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
271 #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
273 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
274 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
277 * For booting Linux, the board info and command line data
278 * have to be in the first 8 MB of memory, since this is
279 * the maximum mapped by the Linux kernel during initialization.
281 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
282 /*-----------------------------------------------------------------------
285 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
286 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
288 #define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
289 #define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
290 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
291 #define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */
293 We have two flash devices connected in parallel.
294 Each device incorporates a Write Buffer of 32 bytes.
296 #define CONFIG_SYS_FLASH_BUFFER_SIZE (2*32)
298 /* Put environment in flash which is much faster to boot than using the EEPROM */
299 #define CONFIG_ENV_IS_IN_FLASH 1
300 #define CONFIG_ENV_ADDR 0x40040000 /* Address of Environment Sector */
301 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */
302 #define CONFIG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */
304 /*-----------------------------------------------------------------------
305 * I2C/EEPROM Configuration
308 #define CONFIG_SYS_I2C_AUDIO_ADDR 0x28 /* Audio volume control */
309 #define CONFIG_SYS_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */
310 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
311 #define CONFIG_SYS_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */
312 #define CONFIG_SYS_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */
313 #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
314 #define CONFIG_SYS_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */
316 #undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */
318 #ifdef CONFIG_USE_FRAM /* use FRAM */
319 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */
320 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
321 #else /* use EEPROM */
322 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
323 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
324 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
325 #endif /* CONFIG_USE_FRAM */
326 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
328 /* List of I2C addresses to be verified by POST */
329 #ifdef CONFIG_USE_FRAM
330 #define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
331 CONFIG_SYS_I2C_SYSMON_ADDR, \
332 CONFIG_SYS_I2C_RTC_ADDR, \
333 CONFIG_SYS_I2C_POWER_A_ADDR, \
334 CONFIG_SYS_I2C_POWER_B_ADDR, \
335 CONFIG_SYS_I2C_KEYBD_ADDR, \
336 CONFIG_SYS_I2C_PICIO_ADDR, \
337 CONFIG_SYS_I2C_EEPROM_ADDR, \
339 #else /* Use EEPROM - which show up on 8 consequtive addresses */
340 #define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
341 CONFIG_SYS_I2C_SYSMON_ADDR, \
342 CONFIG_SYS_I2C_RTC_ADDR, \
343 CONFIG_SYS_I2C_POWER_A_ADDR, \
344 CONFIG_SYS_I2C_POWER_B_ADDR, \
345 CONFIG_SYS_I2C_KEYBD_ADDR, \
346 CONFIG_SYS_I2C_PICIO_ADDR, \
347 CONFIG_SYS_I2C_EEPROM_ADDR+0, \
348 CONFIG_SYS_I2C_EEPROM_ADDR+1, \
349 CONFIG_SYS_I2C_EEPROM_ADDR+2, \
350 CONFIG_SYS_I2C_EEPROM_ADDR+3, \
351 CONFIG_SYS_I2C_EEPROM_ADDR+4, \
352 CONFIG_SYS_I2C_EEPROM_ADDR+5, \
353 CONFIG_SYS_I2C_EEPROM_ADDR+6, \
354 CONFIG_SYS_I2C_EEPROM_ADDR+7, \
356 #endif /* CONFIG_USE_FRAM */
358 /*-----------------------------------------------------------------------
359 * Cache Configuration
361 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
362 #if defined(CONFIG_CMD_KGDB)
363 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
366 /*-----------------------------------------------------------------------
367 * SYPCR - System Protection Control 11-9
368 * SYPCR can only be written once after reset!
369 *-----------------------------------------------------------------------
370 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
372 #if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
373 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
374 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
376 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
379 /*-----------------------------------------------------------------------
380 * SIUMCR - SIU Module Configuration 11-6
381 *-----------------------------------------------------------------------
382 * PCMCIA config., multi-function pin tri-state
384 /* EARB, DBGC and DBPC are initialised by the HCW */
386 #define CONFIG_SYS_SIUMCR (SIUMCR_GB5E)
387 /*#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
389 /*-----------------------------------------------------------------------
390 * TBSCR - Time Base Status and Control 11-26
391 *-----------------------------------------------------------------------
392 * Clear Reference Interrupt Status, Timebase freezing enabled
394 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
396 /*-----------------------------------------------------------------------
397 * PISCR - Periodic Interrupt Status and Control 11-31
398 *-----------------------------------------------------------------------
399 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
401 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
403 /*-----------------------------------------------------------------------
404 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
405 *-----------------------------------------------------------------------
406 * Reset PLL lock status sticky bit, timer expired status bit and timer
407 * interrupt status bit, set PLL multiplication factor !
410 #define CONFIG_SYS_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */
411 #define CONFIG_SYS_PLPRCR \
412 ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
413 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
414 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
415 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
418 #define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*13200000)
420 /*-----------------------------------------------------------------------
421 * SCCR - System Clock and reset Control Register 15-27
422 *-----------------------------------------------------------------------
423 * Set clock output, timebase and RTC source and divider,
424 * power management and some other internal clocks
426 #define SCCR_MASK SCCR_EBDF11
428 #define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
429 SCCR_RTDIV | SCCR_RTSEL | \
430 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
431 SCCR_EBDF00 | SCCR_DFSYNC00 | \
432 SCCR_DFBRG00 | SCCR_DFNL000 | \
433 SCCR_DFNH000 | SCCR_DFLCD100 | \
436 /*-----------------------------------------------------------------------
437 * RTCSC - Real-Time Clock Status and Control Register 11-27
438 *-----------------------------------------------------------------------
440 /* 0x00C3 => 0x0003 */
441 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
444 /*-----------------------------------------------------------------------
445 * RCCR - RISC Controller Configuration Register 19-4
446 *-----------------------------------------------------------------------
448 #define CONFIG_SYS_RCCR 0x0000
450 /*-----------------------------------------------------------------------
451 * RMDS - RISC Microcode Development Support Control Register
452 *-----------------------------------------------------------------------
454 #define CONFIG_SYS_RMDS 0
456 /*-----------------------------------------------------------------------
459 *-----------------------------------------------------------------------
461 #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
463 /*-----------------------------------------------------------------------
465 *-----------------------------------------------------------------------
468 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0x50000000)
469 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
470 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0x54000000)
471 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
472 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0x58000000)
473 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
474 #define CONFIG_SYS_PCMCIA_IO_ADDR (0x5C000000)
475 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
477 /*-----------------------------------------------------------------------
478 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
479 *-----------------------------------------------------------------------
482 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
483 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
485 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
486 #undef CONFIG_IDE_LED /* LED for ide not supported */
487 #undef CONFIG_IDE_RESET /* reset for ide not supported */
489 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
490 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
492 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
494 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
496 /* Offset for data I/O */
497 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
499 /* Offset for normal register accesses */
500 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
502 /* Offset for alternate registers */
503 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
505 #define CONFIG_SUPPORT_VFAT /* enable VFAT support */
507 /*-----------------------------------------------------------------------
509 *-----------------------------------------------------------------------
512 #define CONFIG_SYS_DER 0
515 * Init Memory Controller:
517 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
520 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
521 #define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */
523 /* used to re-map FLASH:
524 * restrict access enough to keep SRAM working (if any)
525 * but not too much to meddle with FLASH accesses
527 #define CONFIG_SYS_REMAP_OR_AM 0xFF000000 /* OR addr mask */
528 #define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
530 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
531 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK)
533 #define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
534 CONFIG_SYS_OR_TIMING_FLASH)
535 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
536 CONFIG_SYS_OR_TIMING_FLASH)
537 /* 16 bit, bank valid */
538 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
540 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
541 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
542 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
547 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
549 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
550 #define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */
551 #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
553 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */
555 #define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
556 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
559 * BR5/OR5: Touch Panel
561 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
563 #define TOUCHPNL_BASE 0x20000000
564 #define TOUCHPNL_OR_AM 0xFFFF8000
565 #define TOUCHPNL_TIMING OR_SCY_0_CLK
567 #define CONFIG_SYS_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
569 #define CONFIG_SYS_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
571 #define CONFIG_SYS_MEMORY_75
572 #undef CONFIG_SYS_MEMORY_7E
573 #undef CONFIG_SYS_MEMORY_8E
576 * Memory Periodic Timer Prescaler
579 /* periodic timer for refresh */
580 #define CONFIG_SYS_MPTPR 0x200
583 * MAMR settings for SDRAM
586 #define CONFIG_SYS_MAMR_8COL 0x80802114
587 #define CONFIG_SYS_MAMR_9COL 0x80904114
590 * MAR setting for SDRAM
592 #define CONFIG_SYS_MAR 0x00000088
594 #endif /* __CONFIG_H */