3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * Configuation settings for the LUBBOCK board.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * High Level Configuration Options
37 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38 #define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */
41 #define CONFIG_SHARP_LM8V31
44 #define BOARD_LATE_INIT 1
46 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
49 * Size of malloc() pool
51 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
52 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
57 #define CONFIG_DRIVER_LAN91C96
58 #define CONFIG_LAN91C96_BASE 0x0C000000
61 * select serial console configuration
63 #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
65 /* allow to overwrite serial and ethaddr */
66 #define CONFIG_ENV_OVERWRITE
68 #define CONFIG_BAUDRATE 115200
70 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT)
72 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
73 #include <cmd_confdefs.h>
75 #define CONFIG_BOOTDELAY 3
76 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
77 #define CONFIG_NETMASK 255.255.0.0
78 #define CONFIG_IPADDR 192.168.0.21
79 #define CONFIG_SERVERIP 192.168.0.250
80 #define CONFIG_BOOTCOMMAND "bootm 80000"
81 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
82 #define CONFIG_CMDLINE_TAG
83 #define CONFIG_TIMESTAMP
85 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
86 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
87 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
91 * Miscellaneous configurable options
93 #define CFG_HUSH_PARSER 1
94 #define CFG_PROMPT_HUSH_PS2 "> "
96 #define CFG_LONGHELP /* undef to save memory */
97 #ifdef CFG_HUSH_PARSER
98 #define CFG_PROMPT "$ " /* Monitor Command Prompt */
100 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
102 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
103 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
104 #define CFG_MAXARGS 16 /* max number of command args */
105 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
106 #define CFG_DEVICE_NULLDEV 1
108 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
109 #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
111 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
113 #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
115 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
116 #define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
118 /* valid baudrates */
119 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
121 #define CFG_MMC_BASE 0xF0000000
126 * The stack sizes are set up in start.S using the settings below
128 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
129 #ifdef CONFIG_USE_IRQ
130 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
131 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
135 * Physical Memory Map
137 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
138 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
139 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
140 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
141 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
142 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
143 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
144 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
145 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
147 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
148 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
149 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
150 #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
151 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
153 #define CFG_DRAM_BASE 0xa0000000
154 #define CFG_DRAM_SIZE 0x04000000
156 #define CFG_FLASH_BASE PHYS_FLASH_1
158 #define FPGA_REGS_BASE_PHYSICAL 0x08000000
163 #define CFG_GPSR0_VAL 0x00008000
164 #define CFG_GPSR1_VAL 0x00FC0382
165 #define CFG_GPSR2_VAL 0x0001FFFF
166 #define CFG_GPCR0_VAL 0x00000000
167 #define CFG_GPCR1_VAL 0x00000000
168 #define CFG_GPCR2_VAL 0x00000000
169 #define CFG_GPDR0_VAL 0x0060A800
170 #define CFG_GPDR1_VAL 0x00FF0382
171 #define CFG_GPDR2_VAL 0x0001C000
172 #define CFG_GAFR0_L_VAL 0x98400000
173 #define CFG_GAFR0_U_VAL 0x00002950
174 #define CFG_GAFR1_L_VAL 0x000A9558
175 #define CFG_GAFR1_U_VAL 0x0005AAAA
176 #define CFG_GAFR2_L_VAL 0xA0000000
177 #define CFG_GAFR2_U_VAL 0x00000002
179 #define CFG_PSSR_VAL 0x20
184 #define CFG_MSC0_VAL 0x23F223F2
185 #define CFG_MSC1_VAL 0x3FF1A441
186 #define CFG_MSC2_VAL 0x7FF97FF1
187 #define CFG_MDCNFG_VAL 0x00001AC9
188 #define CFG_MDREFR_VAL 0x00018018
189 #define CFG_MDMRS_VAL 0x00000000
192 * PCMCIA and CF Interfaces
194 #define CFG_MECR_VAL 0x00000000
195 #define CFG_MCMEM0_VAL 0x00010504
196 #define CFG_MCMEM1_VAL 0x00010504
197 #define CFG_MCATT0_VAL 0x00010504
198 #define CFG_MCATT1_VAL 0x00010504
199 #define CFG_MCIO0_VAL 0x00004715
200 #define CFG_MCIO1_VAL 0x00004715
202 #define _LED 0x08000010
203 #define LED_BLANK 0x08000040
206 * FLASH and environment organization
208 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
209 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
211 /* timeout values are in ticks */
212 #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
213 #define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
215 /* NOTE: many default partitioning schemes assume the kernel starts at the
216 * second sector, not an environment. You have been warned!
218 #define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
219 #define CFG_ENV_IS_IN_FLASH 1
220 #define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
221 #define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
222 #define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
228 #define WHOAMI_OFFSET 0x00
229 #define HEXLED_OFFSET 0x10
230 #define BLANKLED_OFFSET 0x40
231 #define DISCRETELED_OFFSET 0x40
232 #define CNFG_SWITCHES_OFFSET 0x50
233 #define USER_SWITCHES_OFFSET 0x60
234 #define MISC_WR_OFFSET 0x80
235 #define MISC_RD_OFFSET 0x90
236 #define INT_MASK_OFFSET 0xC0
237 #define INT_CLEAR_OFFSET 0xD0
238 #define GP_OFFSET 0x100
240 #endif /* __CONFIG_H */