2 * Copyright (C) 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_SYS_GENERIC_BOARD
12 #define CONFIG_REMAKE_ELF
13 #define CONFIG_FSL_LSCH3
14 #define CONFIG_LS2085A
16 #define CONFIG_FSL_TZPC_BP147
19 #define CONFIG_ARM_ERRATA_828024
20 #define CONFIG_ARM_ERRATA_826974
22 /* We need architecture specific misc initializations */
23 #define CONFIG_ARCH_MISC_INIT
25 /* Link Definitions */
26 #define CONFIG_SYS_TEXT_BASE 0x30100000
29 #define CONFIG_SYS_NO_FLASH
32 #define CONFIG_SUPPORT_RAW_INITRD
34 #define CONFIG_SKIP_LOWLEVEL_INIT
35 #define CONFIG_BOARD_EARLY_INIT_F 1
37 /* Flat Device Tree Definitions */
38 #define CONFIG_OF_LIBFDT
39 #define CONFIG_OF_BOARD_SETUP
41 /* new uImage format support */
43 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
45 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
46 #ifndef CONFIG_SYS_FSL_DDR4
47 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
48 #define CONFIG_SYS_DDR_RAW_TIMING
51 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
54 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
56 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
57 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
62 #define CPU_RELEASE_ADDR secondary_boot_func
64 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
65 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
67 * DDR controller use 0 as the base address for binding.
68 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
70 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
71 #define CONFIG_DP_DDR_CTRL 2
72 #define CONFIG_DP_DDR_NUM_CTRLS 1
74 /* Generic Timer Definitions */
75 #define COUNTER_FREQUENCY 12000000 /* 12MHz */
77 /* Size of malloc() pool */
78 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
81 #define CONFIG_CMD_I2C
82 #define CONFIG_SYS_I2C
83 #define CONFIG_SYS_I2C_MXC
84 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
85 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
88 #define CONFIG_CONS_INDEX 2
89 #define CONFIG_SYS_NS16550
90 #define CONFIG_SYS_NS16550_SERIAL
91 #define CONFIG_SYS_NS16550_REG_SIZE 1
92 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
94 #define CONFIG_BAUDRATE 115200
95 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
98 #define CONFIG_FSL_IFC
101 * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
102 * address 0. But this region is limited to 256MB. To accommodate bigger NOR
103 * flash and other devices, we will map CS0 to 0x580000000 after relocation.
104 * CONFIG_SYS_FLASH_BASE has the final address (core view)
105 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
106 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
107 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
109 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
110 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
111 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
113 #ifndef CONFIG_SYS_NO_FLASH
114 #define CONFIG_FLASH_CFI_DRIVER
115 #define CONFIG_SYS_FLASH_CFI
116 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
117 #define CONFIG_SYS_FLASH_QUIET_TEST
120 #define CONFIG_SYS_NAND_BASE 0x520000000
121 #define CONFIG_SYS_NAND_BASE_PHYS 0x20000000
123 /* Debug Server firmware */
124 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
126 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
129 #define CONFIG_FSL_MC_ENET
130 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
131 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
132 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH (256 * 1024)
133 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000
135 /* Carve out a DDR region which will not be used by u-boot/Linux */
136 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
137 #define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
141 #define CONFIG_PCIE1 /* PCIE controler 1 */
142 #define CONFIG_PCIE2 /* PCIE controler 2 */
143 #define CONFIG_PCIE3 /* PCIE controler 3 */
144 #define CONFIG_PCIE4 /* PCIE controler 4 */
145 #define FSL_PCIE_COMPAT "fsl,20851a-pcie"
147 #define CONFIG_SYS_PCI_64BIT
149 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
150 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
151 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
152 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
154 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
155 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
156 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
158 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
159 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
160 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
162 /* Command line configuration */
163 #define CONFIG_CMD_CACHE
164 #define CONFIG_CMD_BDI
165 #define CONFIG_CMD_DHCP
166 #define CONFIG_CMD_ENV
167 #define CONFIG_CMD_FLASH
168 #define CONFIG_CMD_IMI
169 #define CONFIG_CMD_LOADB
170 #define CONFIG_CMD_MEMORY
171 #define CONFIG_CMD_MII
172 #define CONFIG_CMD_NET
173 #define CONFIG_CMD_PING
174 #define CONFIG_CMD_SAVEENV
175 #define CONFIG_CMD_RUN
176 #define CONFIG_CMD_BOOTD
177 #define CONFIG_CMD_ECHO
178 #define CONFIG_CMD_SOURCE
179 #define CONFIG_CMD_FAT
180 #define CONFIG_DOS_PARTITION
182 /* Miscellaneous configurable options */
183 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
184 #define CONFIG_ARCH_EARLY_INIT_R
186 /* Physical Memory Map */
187 /* fixme: these need to be checked against the board */
188 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
190 #define CONFIG_NR_DRAM_BANKS 3
192 #define CONFIG_HWCONFIG
193 #define HWCONFIG_BUFFER_SIZE 128
195 #define CONFIG_DISPLAY_CPUINFO
197 /* Initial environment variables */
198 #define CONFIG_EXTRA_ENV_SETTINGS \
199 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
200 "loadaddr=0x80100000\0" \
201 "kernel_addr=0x100000\0" \
202 "ramdisk_addr=0x800000\0" \
203 "ramdisk_size=0x2000000\0" \
204 "fdt_high=0xa0000000\0" \
205 "initrd_high=0xffffffffffffffff\0" \
206 "kernel_start=0x581200000\0" \
207 "kernel_load=0xa0000000\0" \
208 "kernel_size=0x1000000\0" \
209 "console=ttyAMA0,38400n8\0"
211 #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
212 "earlycon=uart8250,mmio,0x21c0600,115200 " \
213 "default_hugepagesz=2m hugepagesz=2m " \
215 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
216 "$kernel_size && bootm $kernel_load"
217 #define CONFIG_BOOTDELAY 1
219 /* Monitor Command Prompt */
220 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
221 #define CONFIG_SYS_PROMPT "=> "
222 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
223 sizeof(CONFIG_SYS_PROMPT) + 16)
224 #define CONFIG_SYS_HUSH_PARSER
225 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
226 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
227 #define CONFIG_SYS_LONGHELP
228 #define CONFIG_CMDLINE_EDITING 1
229 #define CONFIG_AUTO_COMPLETE
230 #define CONFIG_SYS_MAXARGS 64 /* max command args */
233 unsigned long get_dram_size_to_hide(void);
236 #define CONFIG_PANIC_HANG /* do not reset board on panic */
238 #endif /* __LS2_COMMON_H */