1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #ifdef CONFIG_FSL_QSPI
13 #ifdef CONFIG_TARGET_LS2081ARDB
14 #define CONFIG_QIXIS_I2C_ACCESS
18 #define I2C_MUX_CH_VOL_MONITOR 0xa
19 #define I2C_VOL_MONITOR_ADDR 0x38
20 #define CONFIG_VOL_MONITOR_IR36021_READ
21 #define CONFIG_VOL_MONITOR_IR36021_SET
23 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
24 #ifndef CONFIG_SPL_BUILD
27 /* step the IR regulator in 5mV increments */
28 #define IR_VDD_STEP_DOWN 5
29 #define IR_VDD_STEP_UP 5
30 /* The lowest and highest voltage allowed for LS2080ARDB */
31 #define VDD_MV_MIN 819
32 #define VDD_MV_MAX 1212
35 unsigned long get_board_sys_clk(void);
38 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
39 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
41 #define CONFIG_DDR_SPD
42 #define CONFIG_DDR_ECC
43 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
44 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
45 #define SPD_EEPROM_ADDRESS1 0x51
46 #define SPD_EEPROM_ADDRESS2 0x52
47 #define SPD_EEPROM_ADDRESS3 0x53
48 #define SPD_EEPROM_ADDRESS4 0x54
49 #define SPD_EEPROM_ADDRESS5 0x55
50 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
51 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
52 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
53 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
54 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
55 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
56 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
60 #define CONFIG_SCSI_AHCI_PLAT
62 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
63 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
65 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
66 #define CONFIG_SYS_SCSI_MAX_LUN 1
67 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
68 CONFIG_SYS_SCSI_MAX_LUN)
70 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
72 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
73 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
74 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
76 #define CONFIG_SYS_NOR0_CSPR \
77 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
81 #define CONFIG_SYS_NOR0_CSPR_EARLY \
82 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
86 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
87 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
88 FTIM0_NOR_TEADC(0x5) | \
90 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
91 FTIM1_NOR_TRAD_NOR(0x1a) |\
92 FTIM1_NOR_TSEQRAD_NOR(0x13))
93 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
94 FTIM2_NOR_TCH(0x4) | \
95 FTIM2_NOR_TWPH(0x0E) | \
97 #define CONFIG_SYS_NOR_FTIM3 0x04000000
98 #define CONFIG_SYS_IFC_CCR 0x01000000
100 #ifdef CONFIG_MTD_NOR_FLASH
101 #define CONFIG_SYS_FLASH_QUIET_TEST
102 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
104 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
105 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
106 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
107 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
109 #define CONFIG_SYS_FLASH_EMPTY_INFO
110 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
111 CONFIG_SYS_FLASH_BASE + 0x40000000}
114 #define CONFIG_NAND_FSL_IFC
115 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
116 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
118 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
119 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
120 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
121 | CSPR_MSEL_NAND /* MSEL = NAND */ \
123 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
125 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
126 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
127 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
128 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
129 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
130 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
131 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
133 #define CONFIG_SYS_NAND_ONFI_DETECTION
135 /* ONFI NAND Flash mode0 Timing Params */
136 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
137 FTIM0_NAND_TWP(0x30) | \
138 FTIM0_NAND_TWCHT(0x0e) | \
139 FTIM0_NAND_TWH(0x14))
140 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
141 FTIM1_NAND_TWBE(0xab) | \
142 FTIM1_NAND_TRR(0x1c) | \
143 FTIM1_NAND_TRP(0x30))
144 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
145 FTIM2_NAND_TREH(0x14) | \
146 FTIM2_NAND_TWHRE(0x3c))
147 #define CONFIG_SYS_NAND_FTIM3 0x0
149 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
150 #define CONFIG_SYS_MAX_NAND_DEVICE 1
151 #define CONFIG_MTD_NAND_VERIFY_WRITE
153 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
154 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
155 #define QIXIS_LBMAP_SWITCH 0x06
156 #define QIXIS_LBMAP_MASK 0x0f
157 #define QIXIS_LBMAP_SHIFT 0
158 #define QIXIS_LBMAP_DFLTBANK 0x00
159 #define QIXIS_LBMAP_ALTBANK 0x04
160 #define QIXIS_LBMAP_NAND 0x09
161 #define QIXIS_RST_CTL_RESET 0x31
162 #define QIXIS_RST_CTL_RESET_EN 0x30
163 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
164 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
165 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
166 #define QIXIS_RCW_SRC_NAND 0x119
167 #define QIXIS_RST_FORCE_MEM 0x01
169 #define CONFIG_SYS_CSPR3_EXT (0x0)
170 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
174 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
179 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
180 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
181 /* QIXIS Timing parameters for IFC CS3 */
182 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
183 FTIM0_GPCM_TEADC(0x0e) | \
184 FTIM0_GPCM_TEAHC(0x0e))
185 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
186 FTIM1_GPCM_TRAD(0x3f))
187 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
188 FTIM2_GPCM_TCH(0xf) | \
189 FTIM2_GPCM_TWP(0x3E))
190 #define CONFIG_SYS_CS3_FTIM3 0x0
192 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
193 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
194 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
195 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
196 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
197 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
198 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
199 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
200 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
201 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
202 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
203 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
204 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
205 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
206 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
207 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
208 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
209 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
211 #define CONFIG_SPL_PAD_TO 0x80000
212 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
213 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
215 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
216 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
217 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
218 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
219 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
220 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
221 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
222 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
223 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
224 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
225 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
226 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
227 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
228 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
229 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
230 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
231 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
234 /* Debug Server firmware */
235 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
236 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
238 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
240 #ifdef CONFIG_TARGET_LS2081ARDB
241 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
242 #define QIXIS_QMAP_MASK 0x07
243 #define QIXIS_QMAP_SHIFT 5
244 #define QIXIS_LBMAP_DFLTBANK 0x00
245 #define QIXIS_LBMAP_QSPI 0x00
246 #define QIXIS_RCW_SRC_QSPI 0x62
247 #define QIXIS_LBMAP_ALTBANK 0x20
248 #define QIXIS_RST_CTL_RESET 0x31
249 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
250 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
251 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
252 #define QIXIS_LBMAP_MASK 0x0f
253 #define QIXIS_RST_CTL_RESET_EN 0x30
259 #ifdef CONFIG_TARGET_LS2081ARDB
260 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
262 #define I2C_MUX_PCA_ADDR 0x75
263 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
265 /* I2C bus multiplexer */
266 #define I2C_MUX_CH_DEFAULT 0x8
269 #if defined(CONFIG_FSL_DSPI)
270 #define CONFIG_SPI_FLASH_STMICRO
277 #ifdef CONFIG_TARGET_LS2081ARDB
278 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
280 #define CONFIG_RTC_DS3231 1
281 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
285 #define CONFIG_SYS_I2C_EEPROM_NXID
286 #define CONFIG_SYS_EEPROM_BUS_NUM 0
288 #define CONFIG_FSL_MEMAC
291 #define CONFIG_PCI_SCAN_SHOW
294 #define BOOT_TARGET_DEVICES(func) \
297 func(SCSI, scsi, 0) \
299 #include <config_distro_bootcmd.h>
301 #ifdef CONFIG_TFABOOT
302 #define QSPI_MC_INIT_CMD \
304 "sf read 0x80640000 0x640000 0x80000; " \
305 "env exists secureboot && " \
306 "esbc_validate 0x80640000 && " \
307 "esbc_validate 0x80680000; " \
308 "sf read 0x80a00000 0xa00000 0x200000; " \
309 "sf read 0x80e00000 0xe00000 0x100000; " \
310 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
311 #define SD_MC_INIT_CMD \
312 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
313 "mmc read 0x80e00000 0x7000 0x800;" \
314 "env exists secureboot && " \
315 "mmc read 0x80640000 0x3200 0x20 && " \
316 "mmc read 0x80680000 0x3400 0x20 && " \
317 "esbc_validate 0x80640000 && " \
318 "esbc_validate 0x80680000 ;" \
319 "fsl_mc start mc 0x80a00000 0x80e00000\0"
320 #define IFC_MC_INIT_CMD \
321 "env exists secureboot && " \
322 "esbc_validate 0x580640000 && " \
323 "esbc_validate 0x580680000; " \
324 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
326 #ifdef CONFIG_QSPI_BOOT
327 #define MC_INIT_CMD \
328 "mcinitcmd=sf probe 0:0; " \
329 "sf read 0x80640000 0x640000 0x80000; " \
330 "env exists secureboot && " \
331 "esbc_validate 0x80640000 && " \
332 "esbc_validate 0x80680000; " \
333 "sf read 0x80a00000 0xa00000 0x200000; " \
334 "sf read 0x80e00000 0xe00000 0x100000; " \
335 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
336 #elif defined(CONFIG_SD_BOOT)
337 #define MC_INIT_CMD \
338 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
339 "mmc read 0x80e00000 0x7000 0x800;" \
340 "env exists secureboot && " \
341 "mmc read 0x80640000 0x3200 0x20 && " \
342 "mmc read 0x80680000 0x3400 0x20 && " \
343 "esbc_validate 0x80640000 && " \
344 "esbc_validate 0x80680000 ;" \
345 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
346 "mcmemsize=0x70000000\0"
348 #define MC_INIT_CMD \
349 "mcinitcmd=env exists secureboot && " \
350 "esbc_validate 0x580640000 && " \
351 "esbc_validate 0x580680000; " \
352 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
356 /* Initial environment variables */
357 #undef CONFIG_EXTRA_ENV_SETTINGS
358 #ifdef CONFIG_TFABOOT
359 #define CONFIG_EXTRA_ENV_SETTINGS \
360 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
361 "ramdisk_addr=0x800000\0" \
362 "ramdisk_size=0x2000000\0" \
363 "fdt_high=0xa0000000\0" \
364 "initrd_high=0xffffffffffffffff\0" \
365 "fdt_addr=0x64f00000\0" \
366 "kernel_addr=0x581000000\0" \
367 "kernel_start=0x1000000\0" \
368 "kernelheader_start=0x800000\0" \
369 "scriptaddr=0x80000000\0" \
370 "scripthdraddr=0x80080000\0" \
371 "fdtheader_addr_r=0x80100000\0" \
372 "kernelheader_addr_r=0x80200000\0" \
373 "kernelheader_addr=0x580600000\0" \
374 "kernel_addr_r=0x81000000\0" \
375 "kernelheader_size=0x40000\0" \
376 "fdt_addr_r=0x90000000\0" \
377 "load_addr=0xa0000000\0" \
378 "kernel_size=0x2800000\0" \
379 "kernel_addr_sd=0x8000\0" \
380 "kernel_size_sd=0x14000\0" \
381 "console=ttyAMA0,38400n8\0" \
382 "mcmemsize=0x70000000\0" \
383 "sd_bootcmd=echo Trying load from SD ..;" \
384 "mmcinfo; mmc read $load_addr " \
385 "$kernel_addr_sd $kernel_size_sd && " \
386 "bootm $load_addr#$board\0" \
389 "boot_scripts=ls2088ardb_boot.scr\0" \
390 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
391 "scan_dev_for_boot_part=" \
392 "part list ${devtype} ${devnum} devplist; " \
393 "env exists devplist || setenv devplist 1; " \
394 "for distro_bootpart in ${devplist}; do " \
395 "if fstype ${devtype} " \
396 "${devnum}:${distro_bootpart} " \
397 "bootfstype; then " \
398 "run scan_dev_for_boot; " \
402 "load ${devtype} ${devnum}:${distro_bootpart} " \
403 "${scriptaddr} ${prefix}${script}; " \
404 "env exists secureboot && load ${devtype} " \
405 "${devnum}:${distro_bootpart} " \
406 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
407 "&& esbc_validate ${scripthdraddr};" \
408 "source ${scriptaddr}\0" \
409 "qspi_bootcmd=echo Trying load from qspi..;" \
410 "sf probe && sf read $load_addr " \
411 "$kernel_start $kernel_size ; env exists secureboot &&" \
412 "sf read $kernelheader_addr_r $kernelheader_start " \
413 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
414 " bootm $load_addr#$board\0" \
415 "nor_bootcmd=echo Trying load from nor..;" \
416 "cp.b $kernel_addr $load_addr " \
417 "$kernel_size ; env exists secureboot && " \
418 "cp.b $kernelheader_addr $kernelheader_addr_r " \
419 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
420 "bootm $load_addr#$board\0"
422 #define CONFIG_EXTRA_ENV_SETTINGS \
423 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
424 "ramdisk_addr=0x800000\0" \
425 "ramdisk_size=0x2000000\0" \
426 "fdt_high=0xa0000000\0" \
427 "initrd_high=0xffffffffffffffff\0" \
428 "fdt_addr=0x64f00000\0" \
429 "kernel_addr=0x581000000\0" \
430 "kernel_start=0x1000000\0" \
431 "kernelheader_start=0x600000\0" \
432 "scriptaddr=0x80000000\0" \
433 "scripthdraddr=0x80080000\0" \
434 "fdtheader_addr_r=0x80100000\0" \
435 "kernelheader_addr_r=0x80200000\0" \
436 "kernelheader_addr=0x580600000\0" \
437 "kernel_addr_r=0x81000000\0" \
438 "kernelheader_size=0x40000\0" \
439 "fdt_addr_r=0x90000000\0" \
440 "load_addr=0xa0000000\0" \
441 "kernel_size=0x2800000\0" \
442 "kernel_addr_sd=0x8000\0" \
443 "kernel_size_sd=0x14000\0" \
444 "console=ttyAMA0,38400n8\0" \
445 "mcmemsize=0x70000000\0" \
446 "sd_bootcmd=echo Trying load from SD ..;" \
447 "mmcinfo; mmc read $load_addr " \
448 "$kernel_addr_sd $kernel_size_sd && " \
449 "bootm $load_addr#$board\0" \
452 "boot_scripts=ls2088ardb_boot.scr\0" \
453 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
454 "scan_dev_for_boot_part=" \
455 "part list ${devtype} ${devnum} devplist; " \
456 "env exists devplist || setenv devplist 1; " \
457 "for distro_bootpart in ${devplist}; do " \
458 "if fstype ${devtype} " \
459 "${devnum}:${distro_bootpart} " \
460 "bootfstype; then " \
461 "run scan_dev_for_boot; " \
465 "load ${devtype} ${devnum}:${distro_bootpart} " \
466 "${scriptaddr} ${prefix}${script}; " \
467 "env exists secureboot && load ${devtype} " \
468 "${devnum}:${distro_bootpart} " \
469 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
470 "env exists secureboot " \
471 "&& esbc_validate ${scripthdraddr};" \
472 "source ${scriptaddr}\0" \
473 "qspi_bootcmd=echo Trying load from qspi..;" \
474 "sf probe && sf read $load_addr " \
475 "$kernel_start $kernel_size ; env exists secureboot &&" \
476 "sf read $kernelheader_addr_r $kernelheader_start " \
477 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
478 " bootm $load_addr#$board\0" \
479 "nor_bootcmd=echo Trying load from nor..;" \
480 "cp.b $kernel_addr $load_addr " \
481 "$kernel_size ; env exists secureboot && " \
482 "cp.b $kernelheader_addr $kernelheader_addr_r " \
483 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
484 "bootm $load_addr#$board\0"
487 #ifdef CONFIG_TFABOOT
488 #define QSPI_NOR_BOOTCOMMAND \
490 "sf read 0x806c0000 0x6c0000 0x40000; " \
491 "env exists mcinitcmd && env exists secureboot "\
492 "&& esbc_validate 0x806c0000; " \
493 "sf read 0x80d00000 0xd00000 0x100000; " \
494 "env exists mcinitcmd && " \
495 "fsl_mc lazyapply dpl 0x80d00000; " \
496 "run distro_bootcmd;run qspi_bootcmd; " \
497 "env exists secureboot && esbc_halt;"
499 /* Try to boot an on-SD kernel first, then do normal distro boot */
500 #define SD_BOOTCOMMAND \
501 "env exists mcinitcmd && env exists secureboot "\
502 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
503 "&& esbc_validate $load_addr; " \
504 "env exists mcinitcmd && run mcinitcmd " \
505 "&& mmc read 0x80d00000 0x6800 0x800 " \
506 "&& fsl_mc lazyapply dpl 0x80d00000; " \
507 "run distro_bootcmd;run sd_bootcmd; " \
508 "env exists secureboot && esbc_halt;"
510 /* Try to boot an on-NOR kernel first, then do normal distro boot */
511 #define IFC_NOR_BOOTCOMMAND \
512 "env exists mcinitcmd && env exists secureboot "\
513 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
514 "&& fsl_mc lazyapply dpl 0x580d00000;" \
515 "run distro_bootcmd;run nor_bootcmd; " \
516 "env exists secureboot && esbc_halt;"
518 #undef CONFIG_BOOTCOMMAND
519 #ifdef CONFIG_QSPI_BOOT
520 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
521 #define CONFIG_BOOTCOMMAND \
523 "sf read 0x806c0000 0x6c0000 0x40000; " \
524 "env exists mcinitcmd && env exists secureboot "\
525 "&& esbc_validate 0x806C0000; " \
526 "sf read 0x80d00000 0xd00000 0x100000; " \
527 "env exists mcinitcmd && " \
528 "fsl_mc lazyapply dpl 0x80d00000; " \
529 "run distro_bootcmd;run qspi_bootcmd; " \
530 "env exists secureboot && esbc_halt;"
531 #elif defined(CONFIG_SD_BOOT)
532 /* Try to boot an on-SD kernel first, then do normal distro boot */
533 #define CONFIG_BOOTCOMMAND \
534 "env exists mcinitcmd && env exists secureboot "\
535 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
536 "&& esbc_validate $load_addr; " \
537 "env exists mcinitcmd && run mcinitcmd " \
538 "&& mmc read 0x88000000 0x6800 0x800 " \
539 "&& fsl_mc lazyapply dpl 0x88000000; " \
540 "run distro_bootcmd;run sd_bootcmd; " \
541 "env exists secureboot && esbc_halt;"
543 /* Try to boot an on-NOR kernel first, then do normal distro boot */
544 #define CONFIG_BOOTCOMMAND \
545 "env exists mcinitcmd && env exists secureboot "\
546 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
547 "&& fsl_mc lazyapply dpl 0x580d00000;" \
548 "run distro_bootcmd;run nor_bootcmd; " \
549 "env exists secureboot && esbc_halt;"
553 /* MAC/PHY configuration */
554 #define CORTINA_PHY_ADDR1 0x10
555 #define CORTINA_PHY_ADDR2 0x11
556 #define CORTINA_PHY_ADDR3 0x12
557 #define CORTINA_PHY_ADDR4 0x13
558 #define AQ_PHY_ADDR1 0x00
559 #define AQ_PHY_ADDR2 0x01
560 #define AQ_PHY_ADDR3 0x02
561 #define AQ_PHY_ADDR4 0x03
562 #define AQR405_IRQ_MASK 0x36
563 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
565 #include <asm/fsl_secure_boot.h>
567 #endif /* __LS2_RDB_H */