1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #ifdef CONFIG_FSL_QSPI
13 #ifdef CONFIG_TARGET_LS2081ARDB
14 #define CONFIG_QIXIS_I2C_ACCESS
16 #if !CONFIG_IS_ENABLED(DM_I2C)
17 #define CONFIG_SYS_I2C_EARLY_INIT
21 #define I2C_MUX_CH_VOL_MONITOR 0xa
22 #define I2C_VOL_MONITOR_ADDR 0x38
23 #define CONFIG_VOL_MONITOR_IR36021_READ
24 #define CONFIG_VOL_MONITOR_IR36021_SET
26 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
27 #ifndef CONFIG_SPL_BUILD
30 /* step the IR regulator in 5mV increments */
31 #define IR_VDD_STEP_DOWN 5
32 #define IR_VDD_STEP_UP 5
33 /* The lowest and highest voltage allowed for LS2080ARDB */
34 #define VDD_MV_MIN 819
35 #define VDD_MV_MAX 1212
38 unsigned long get_board_sys_clk(void);
41 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
42 #define CONFIG_DDR_CLK_FREQ 133333333
43 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
45 #define CONFIG_DDR_SPD
46 #define CONFIG_DDR_ECC
47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
49 #define SPD_EEPROM_ADDRESS1 0x51
50 #define SPD_EEPROM_ADDRESS2 0x52
51 #define SPD_EEPROM_ADDRESS3 0x53
52 #define SPD_EEPROM_ADDRESS4 0x54
53 #define SPD_EEPROM_ADDRESS5 0x55
54 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
55 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
56 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
57 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
58 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
59 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
60 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
64 #define CONFIG_SCSI_AHCI_PLAT
66 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
67 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
69 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
70 #define CONFIG_SYS_SCSI_MAX_LUN 1
71 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
72 CONFIG_SYS_SCSI_MAX_LUN)
74 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
76 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
77 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
78 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
80 #define CONFIG_SYS_NOR0_CSPR \
81 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
85 #define CONFIG_SYS_NOR0_CSPR_EARLY \
86 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
90 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
91 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
92 FTIM0_NOR_TEADC(0x5) | \
94 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
95 FTIM1_NOR_TRAD_NOR(0x1a) |\
96 FTIM1_NOR_TSEQRAD_NOR(0x13))
97 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
98 FTIM2_NOR_TCH(0x4) | \
99 FTIM2_NOR_TWPH(0x0E) | \
101 #define CONFIG_SYS_NOR_FTIM3 0x04000000
102 #define CONFIG_SYS_IFC_CCR 0x01000000
104 #ifdef CONFIG_MTD_NOR_FLASH
105 #define CONFIG_SYS_FLASH_QUIET_TEST
106 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
108 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
109 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
113 #define CONFIG_SYS_FLASH_EMPTY_INFO
114 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
115 CONFIG_SYS_FLASH_BASE + 0x40000000}
118 #define CONFIG_NAND_FSL_IFC
119 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
120 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
122 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
123 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
124 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
125 | CSPR_MSEL_NAND /* MSEL = NAND */ \
127 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
129 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
130 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
131 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
132 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
133 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
134 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
135 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
137 #define CONFIG_SYS_NAND_ONFI_DETECTION
139 /* ONFI NAND Flash mode0 Timing Params */
140 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
141 FTIM0_NAND_TWP(0x30) | \
142 FTIM0_NAND_TWCHT(0x0e) | \
143 FTIM0_NAND_TWH(0x14))
144 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
145 FTIM1_NAND_TWBE(0xab) | \
146 FTIM1_NAND_TRR(0x1c) | \
147 FTIM1_NAND_TRP(0x30))
148 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
149 FTIM2_NAND_TREH(0x14) | \
150 FTIM2_NAND_TWHRE(0x3c))
151 #define CONFIG_SYS_NAND_FTIM3 0x0
153 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
154 #define CONFIG_SYS_MAX_NAND_DEVICE 1
155 #define CONFIG_MTD_NAND_VERIFY_WRITE
157 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
158 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
159 #define QIXIS_LBMAP_SWITCH 0x06
160 #define QIXIS_LBMAP_MASK 0x0f
161 #define QIXIS_LBMAP_SHIFT 0
162 #define QIXIS_LBMAP_DFLTBANK 0x00
163 #define QIXIS_LBMAP_ALTBANK 0x04
164 #define QIXIS_LBMAP_NAND 0x09
165 #define QIXIS_RST_CTL_RESET 0x31
166 #define QIXIS_RST_CTL_RESET_EN 0x30
167 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
168 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
169 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
170 #define QIXIS_RCW_SRC_NAND 0x119
171 #define QIXIS_RST_FORCE_MEM 0x01
173 #define CONFIG_SYS_CSPR3_EXT (0x0)
174 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
178 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
183 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
184 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
185 /* QIXIS Timing parameters for IFC CS3 */
186 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
187 FTIM0_GPCM_TEADC(0x0e) | \
188 FTIM0_GPCM_TEAHC(0x0e))
189 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
190 FTIM1_GPCM_TRAD(0x3f))
191 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
192 FTIM2_GPCM_TCH(0xf) | \
193 FTIM2_GPCM_TWP(0x3E))
194 #define CONFIG_SYS_CS3_FTIM3 0x0
196 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
197 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
198 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
199 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
200 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
201 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
202 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
203 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
204 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
205 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
206 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
207 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
208 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
209 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
210 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
211 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
212 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
213 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
215 #define CONFIG_SPL_PAD_TO 0x80000
216 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
217 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
219 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
220 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
221 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
222 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
223 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
224 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
225 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
226 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
227 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
228 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
229 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
230 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
231 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
232 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
233 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
234 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
235 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
238 /* Debug Server firmware */
239 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
240 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
242 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
244 #ifdef CONFIG_TARGET_LS2081ARDB
245 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
246 #define QIXIS_QMAP_MASK 0x07
247 #define QIXIS_QMAP_SHIFT 5
248 #define QIXIS_LBMAP_DFLTBANK 0x00
249 #define QIXIS_LBMAP_QSPI 0x00
250 #define QIXIS_RCW_SRC_QSPI 0x62
251 #define QIXIS_LBMAP_ALTBANK 0x20
252 #define QIXIS_RST_CTL_RESET 0x31
253 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
254 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
255 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
256 #define QIXIS_LBMAP_MASK 0x0f
257 #define QIXIS_RST_CTL_RESET_EN 0x30
263 #ifdef CONFIG_TARGET_LS2081ARDB
264 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
266 #define I2C_MUX_PCA_ADDR 0x75
267 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
269 /* I2C bus multiplexer */
270 #define I2C_MUX_CH_DEFAULT 0x8
273 #if defined(CONFIG_FSL_DSPI)
274 #define CONFIG_SPI_FLASH_STMICRO
281 #ifdef CONFIG_TARGET_LS2081ARDB
282 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
284 #define CONFIG_RTC_DS3231 1
285 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
289 #define CONFIG_SYS_I2C_EEPROM_NXID
290 #define CONFIG_SYS_EEPROM_BUS_NUM 0
291 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
292 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
293 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
294 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
296 #define CONFIG_FSL_MEMAC
299 #define CONFIG_PCI_SCAN_SHOW
302 #define BOOT_TARGET_DEVICES(func) \
305 func(SCSI, scsi, 0) \
307 #include <config_distro_bootcmd.h>
309 #ifdef CONFIG_TFABOOT
310 #define QSPI_MC_INIT_CMD \
312 "sf read 0x80640000 0x640000 0x80000; " \
313 "env exists secureboot && " \
314 "esbc_validate 0x80640000 && " \
315 "esbc_validate 0x80680000; " \
316 "sf read 0x80a00000 0xa00000 0x200000; " \
317 "sf read 0x80e00000 0xe00000 0x100000; " \
318 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
319 #define SD_MC_INIT_CMD \
320 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
321 "mmc read 0x80e00000 0x7000 0x800;" \
322 "env exists secureboot && " \
323 "mmc read 0x80640000 0x3200 0x20 && " \
324 "mmc read 0x80680000 0x3400 0x20 && " \
325 "esbc_validate 0x80640000 && " \
326 "esbc_validate 0x80680000 ;" \
327 "fsl_mc start mc 0x80a00000 0x80e00000\0"
328 #define IFC_MC_INIT_CMD \
329 "env exists secureboot && " \
330 "esbc_validate 0x580640000 && " \
331 "esbc_validate 0x580680000; " \
332 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
334 #ifdef CONFIG_QSPI_BOOT
335 #define MC_INIT_CMD \
336 "mcinitcmd=sf probe 0:0; " \
337 "sf read 0x80640000 0x640000 0x80000; " \
338 "env exists secureboot && " \
339 "esbc_validate 0x80640000 && " \
340 "esbc_validate 0x80680000; " \
341 "sf read 0x80a00000 0xa00000 0x200000; " \
342 "sf read 0x80e00000 0xe00000 0x100000; " \
343 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
344 #elif defined(CONFIG_SD_BOOT)
345 #define MC_INIT_CMD \
346 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
347 "mmc read 0x80e00000 0x7000 0x800;" \
348 "env exists secureboot && " \
349 "mmc read 0x80640000 0x3200 0x20 && " \
350 "mmc read 0x80680000 0x3400 0x20 && " \
351 "esbc_validate 0x80640000 && " \
352 "esbc_validate 0x80680000 ;" \
353 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
354 "mcmemsize=0x70000000\0"
356 #define MC_INIT_CMD \
357 "mcinitcmd=env exists secureboot && " \
358 "esbc_validate 0x580640000 && " \
359 "esbc_validate 0x580680000; " \
360 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
364 /* Initial environment variables */
365 #undef CONFIG_EXTRA_ENV_SETTINGS
366 #ifdef CONFIG_TFABOOT
367 #define CONFIG_EXTRA_ENV_SETTINGS \
368 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
369 "ramdisk_addr=0x800000\0" \
370 "ramdisk_size=0x2000000\0" \
371 "fdt_high=0xa0000000\0" \
372 "initrd_high=0xffffffffffffffff\0" \
373 "fdt_addr=0x64f00000\0" \
374 "kernel_addr=0x581000000\0" \
375 "kernel_start=0x1000000\0" \
376 "kernelheader_start=0x800000\0" \
377 "scriptaddr=0x80000000\0" \
378 "scripthdraddr=0x80080000\0" \
379 "fdtheader_addr_r=0x80100000\0" \
380 "kernelheader_addr_r=0x80200000\0" \
381 "kernelheader_addr=0x580600000\0" \
382 "kernel_addr_r=0x81000000\0" \
383 "kernelheader_size=0x40000\0" \
384 "fdt_addr_r=0x90000000\0" \
385 "load_addr=0xa0000000\0" \
386 "kernel_size=0x2800000\0" \
387 "kernel_addr_sd=0x8000\0" \
388 "kernel_size_sd=0x14000\0" \
389 "console=ttyAMA0,38400n8\0" \
390 "mcmemsize=0x70000000\0" \
391 "sd_bootcmd=echo Trying load from SD ..;" \
392 "mmcinfo; mmc read $load_addr " \
393 "$kernel_addr_sd $kernel_size_sd && " \
394 "bootm $load_addr#$board\0" \
397 "boot_scripts=ls2088ardb_boot.scr\0" \
398 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
399 "scan_dev_for_boot_part=" \
400 "part list ${devtype} ${devnum} devplist; " \
401 "env exists devplist || setenv devplist 1; " \
402 "for distro_bootpart in ${devplist}; do " \
403 "if fstype ${devtype} " \
404 "${devnum}:${distro_bootpart} " \
405 "bootfstype; then " \
406 "run scan_dev_for_boot; " \
410 "load ${devtype} ${devnum}:${distro_bootpart} " \
411 "${scriptaddr} ${prefix}${script}; " \
412 "env exists secureboot && load ${devtype} " \
413 "${devnum}:${distro_bootpart} " \
414 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
415 "&& esbc_validate ${scripthdraddr};" \
416 "source ${scriptaddr}\0" \
417 "qspi_bootcmd=echo Trying load from qspi..;" \
418 "sf probe && sf read $load_addr " \
419 "$kernel_start $kernel_size ; env exists secureboot &&" \
420 "sf read $kernelheader_addr_r $kernelheader_start " \
421 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
422 " bootm $load_addr#$board\0" \
423 "nor_bootcmd=echo Trying load from nor..;" \
424 "cp.b $kernel_addr $load_addr " \
425 "$kernel_size ; env exists secureboot && " \
426 "cp.b $kernelheader_addr $kernelheader_addr_r " \
427 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
428 "bootm $load_addr#$board\0"
430 #define CONFIG_EXTRA_ENV_SETTINGS \
431 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
432 "ramdisk_addr=0x800000\0" \
433 "ramdisk_size=0x2000000\0" \
434 "fdt_high=0xa0000000\0" \
435 "initrd_high=0xffffffffffffffff\0" \
436 "fdt_addr=0x64f00000\0" \
437 "kernel_addr=0x581000000\0" \
438 "kernel_start=0x1000000\0" \
439 "kernelheader_start=0x600000\0" \
440 "scriptaddr=0x80000000\0" \
441 "scripthdraddr=0x80080000\0" \
442 "fdtheader_addr_r=0x80100000\0" \
443 "kernelheader_addr_r=0x80200000\0" \
444 "kernelheader_addr=0x580600000\0" \
445 "kernel_addr_r=0x81000000\0" \
446 "kernelheader_size=0x40000\0" \
447 "fdt_addr_r=0x90000000\0" \
448 "load_addr=0xa0000000\0" \
449 "kernel_size=0x2800000\0" \
450 "kernel_addr_sd=0x8000\0" \
451 "kernel_size_sd=0x14000\0" \
452 "console=ttyAMA0,38400n8\0" \
453 "mcmemsize=0x70000000\0" \
454 "sd_bootcmd=echo Trying load from SD ..;" \
455 "mmcinfo; mmc read $load_addr " \
456 "$kernel_addr_sd $kernel_size_sd && " \
457 "bootm $load_addr#$board\0" \
460 "boot_scripts=ls2088ardb_boot.scr\0" \
461 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
462 "scan_dev_for_boot_part=" \
463 "part list ${devtype} ${devnum} devplist; " \
464 "env exists devplist || setenv devplist 1; " \
465 "for distro_bootpart in ${devplist}; do " \
466 "if fstype ${devtype} " \
467 "${devnum}:${distro_bootpart} " \
468 "bootfstype; then " \
469 "run scan_dev_for_boot; " \
473 "load ${devtype} ${devnum}:${distro_bootpart} " \
474 "${scriptaddr} ${prefix}${script}; " \
475 "env exists secureboot && load ${devtype} " \
476 "${devnum}:${distro_bootpart} " \
477 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
478 "env exists secureboot " \
479 "&& esbc_validate ${scripthdraddr};" \
480 "source ${scriptaddr}\0" \
481 "qspi_bootcmd=echo Trying load from qspi..;" \
482 "sf probe && sf read $load_addr " \
483 "$kernel_start $kernel_size ; env exists secureboot &&" \
484 "sf read $kernelheader_addr_r $kernelheader_start " \
485 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
486 " bootm $load_addr#$board\0" \
487 "nor_bootcmd=echo Trying load from nor..;" \
488 "cp.b $kernel_addr $load_addr " \
489 "$kernel_size ; env exists secureboot && " \
490 "cp.b $kernelheader_addr $kernelheader_addr_r " \
491 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
492 "bootm $load_addr#$board\0"
495 #ifdef CONFIG_TFABOOT
496 #define QSPI_NOR_BOOTCOMMAND \
498 "sf read 0x806c0000 0x6c0000 0x40000; " \
499 "env exists mcinitcmd && env exists secureboot "\
500 "&& esbc_validate 0x806c0000; " \
501 "sf read 0x80d00000 0xd00000 0x100000; " \
502 "env exists mcinitcmd && " \
503 "fsl_mc lazyapply dpl 0x80d00000; " \
504 "run distro_bootcmd;run qspi_bootcmd; " \
505 "env exists secureboot && esbc_halt;"
507 /* Try to boot an on-SD kernel first, then do normal distro boot */
508 #define SD_BOOTCOMMAND \
509 "env exists mcinitcmd && env exists secureboot "\
510 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
511 "&& esbc_validate $load_addr; " \
512 "env exists mcinitcmd && run mcinitcmd " \
513 "&& mmc read 0x80d00000 0x6800 0x800 " \
514 "&& fsl_mc lazyapply dpl 0x80d00000; " \
515 "run distro_bootcmd;run sd_bootcmd; " \
516 "env exists secureboot && esbc_halt;"
518 /* Try to boot an on-NOR kernel first, then do normal distro boot */
519 #define IFC_NOR_BOOTCOMMAND \
520 "env exists mcinitcmd && env exists secureboot "\
521 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
522 "&& fsl_mc lazyapply dpl 0x580d00000;" \
523 "run distro_bootcmd;run nor_bootcmd; " \
524 "env exists secureboot && esbc_halt;"
526 #undef CONFIG_BOOTCOMMAND
527 #ifdef CONFIG_QSPI_BOOT
528 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
529 #define CONFIG_BOOTCOMMAND \
531 "sf read 0x806c0000 0x6c0000 0x40000; " \
532 "env exists mcinitcmd && env exists secureboot "\
533 "&& esbc_validate 0x806C0000; " \
534 "sf read 0x80d00000 0xd00000 0x100000; " \
535 "env exists mcinitcmd && " \
536 "fsl_mc lazyapply dpl 0x80d00000; " \
537 "run distro_bootcmd;run qspi_bootcmd; " \
538 "env exists secureboot && esbc_halt;"
539 #elif defined(CONFIG_SD_BOOT)
540 /* Try to boot an on-SD kernel first, then do normal distro boot */
541 #define CONFIG_BOOTCOMMAND \
542 "env exists mcinitcmd && env exists secureboot "\
543 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
544 "&& esbc_validate $load_addr; " \
545 "env exists mcinitcmd && run mcinitcmd " \
546 "&& mmc read 0x88000000 0x6800 0x800 " \
547 "&& fsl_mc lazyapply dpl 0x88000000; " \
548 "run distro_bootcmd;run sd_bootcmd; " \
549 "env exists secureboot && esbc_halt;"
551 /* Try to boot an on-NOR kernel first, then do normal distro boot */
552 #define CONFIG_BOOTCOMMAND \
553 "env exists mcinitcmd && env exists secureboot "\
554 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
555 "&& fsl_mc lazyapply dpl 0x580d00000;" \
556 "run distro_bootcmd;run nor_bootcmd; " \
557 "env exists secureboot && esbc_halt;"
561 /* MAC/PHY configuration */
562 #define CORTINA_PHY_ADDR1 0x10
563 #define CORTINA_PHY_ADDR2 0x11
564 #define CORTINA_PHY_ADDR3 0x12
565 #define CORTINA_PHY_ADDR4 0x13
566 #define AQ_PHY_ADDR1 0x00
567 #define AQ_PHY_ADDR2 0x01
568 #define AQ_PHY_ADDR3 0x02
569 #define AQ_PHY_ADDR4 0x03
570 #define AQR405_IRQ_MASK 0x36
571 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
573 #include <asm/fsl_secure_boot.h>
575 #endif /* __LS2_RDB_H */