include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #ifdef CONFIG_TARGET_LS2081ARDB
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16 #endif
  17
  18 #define I2C_MUX_CH_VOL_MONITOR          0xa
  19 #define I2C_VOL_MONITOR_ADDR            0x38
  20 #define CONFIG_VOL_MONITOR_IR36021_READ
  21 #define CONFIG_VOL_MONITOR_IR36021_SET
  22
  23 #define CONFIG_VID_FLS_ENV              "ls2080ardb_vdd_mv"
  24 #ifndef CONFIG_SPL_BUILD
  25 #define CONFIG_VID
  26 #endif
  27 /* step the IR regulator in 5mV increments */
  28 #define IR_VDD_STEP_DOWN                5
  29 #define IR_VDD_STEP_UP                  5
  30 /* The lowest and highest voltage allowed for LS2080ARDB */
  31 #define VDD_MV_MIN                      819
  32 #define VDD_MV_MAX                      1212
  33
  34 #ifndef __ASSEMBLY__
  35 unsigned long get_board_sys_clk(void);
  36 #endif
  37
  38 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  39 #define CONFIG_DDR_CLK_FREQ             133333333
  40 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  41
  42 #define CONFIG_DDR_SPD
  43 #define CONFIG_DDR_ECC
  44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  45 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  46 #define SPD_EEPROM_ADDRESS1     0x51
  47 #define SPD_EEPROM_ADDRESS2     0x52
  48 #define SPD_EEPROM_ADDRESS3     0x53
  49 #define SPD_EEPROM_ADDRESS4     0x54
  50 #define SPD_EEPROM_ADDRESS5     0x55
  51 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  52 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  53 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  54 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  55 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  56 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  57 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  58 #endif
  59
  60 /* SATA */
  61 #define CONFIG_SCSI_AHCI_PLAT
  62
  63 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  64 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  65
  66 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  67 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  68 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  69                                                 CONFIG_SYS_SCSI_MAX_LUN)
  70
  71 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  72
  73 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  74 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  75 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  76
  77 #define CONFIG_SYS_NOR0_CSPR                                    \
  78         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  79         CSPR_PORT_SIZE_16                                       | \
  80         CSPR_MSEL_NOR                                           | \
  81         CSPR_V)
  82 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  83         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  84         CSPR_PORT_SIZE_16                                       | \
  85         CSPR_MSEL_NOR                                           | \
  86         CSPR_V)
  87 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  88 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  89                                 FTIM0_NOR_TEADC(0x5) | \
  90                                 FTIM0_NOR_TEAHC(0x5))
  91 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  92                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  93                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  94 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  95                                 FTIM2_NOR_TCH(0x4) | \
  96                                 FTIM2_NOR_TWPH(0x0E) | \
  97                                 FTIM2_NOR_TWP(0x1c))
  98 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  99 #define CONFIG_SYS_IFC_CCR      0x01000000
 100
 101 #ifdef CONFIG_MTD_NOR_FLASH
 102 #define CONFIG_SYS_FLASH_QUIET_TEST
 103 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 104
 105 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 106 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 107 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 108 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 109
 110 #define CONFIG_SYS_FLASH_EMPTY_INFO
 111 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 112                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 113 #endif
 114
 115 #define CONFIG_NAND_FSL_IFC
 116 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 117 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 118
 119 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 120 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 121                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 122                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 123                                 | CSPR_V)
 124 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 125
 126 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 127                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 128                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 129                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 130                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 131                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 132                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 133
 134 #define CONFIG_SYS_NAND_ONFI_DETECTION
 135
 136 /* ONFI NAND Flash mode0 Timing Params */
 137 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 138                                         FTIM0_NAND_TWP(0x30)   | \
 139                                         FTIM0_NAND_TWCHT(0x0e) | \
 140                                         FTIM0_NAND_TWH(0x14))
 141 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 142                                         FTIM1_NAND_TWBE(0xab)  | \
 143                                         FTIM1_NAND_TRR(0x1c)   | \
 144                                         FTIM1_NAND_TRP(0x30))
 145 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 146                                         FTIM2_NAND_TREH(0x14) | \
 147                                         FTIM2_NAND_TWHRE(0x3c))
 148 #define CONFIG_SYS_NAND_FTIM3           0x0
 149
 150 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 151 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 152 #define CONFIG_MTD_NAND_VERIFY_WRITE
 153
 154 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 155 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 156 #define QIXIS_LBMAP_SWITCH              0x06
 157 #define QIXIS_LBMAP_MASK                0x0f
 158 #define QIXIS_LBMAP_SHIFT               0
 159 #define QIXIS_LBMAP_DFLTBANK            0x00
 160 #define QIXIS_LBMAP_ALTBANK             0x04
 161 #define QIXIS_LBMAP_NAND                0x09
 162 #define QIXIS_RST_CTL_RESET             0x31
 163 #define QIXIS_RST_CTL_RESET_EN          0x30
 164 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 165 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 166 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 167 #define QIXIS_RCW_SRC_NAND              0x119
 168 #define QIXIS_RST_FORCE_MEM             0x01
 169
 170 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 171 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 172                                 | CSPR_PORT_SIZE_8 \
 173                                 | CSPR_MSEL_GPCM \
 174                                 | CSPR_V)
 175 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 176                                 | CSPR_PORT_SIZE_8 \
 177                                 | CSPR_MSEL_GPCM \
 178                                 | CSPR_V)
 179
 180 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 181 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 182 /* QIXIS Timing parameters for IFC CS3 */
 183 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 184                                         FTIM0_GPCM_TEADC(0x0e) | \
 185                                         FTIM0_GPCM_TEAHC(0x0e))
 186 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 187                                         FTIM1_GPCM_TRAD(0x3f))
 188 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 189                                         FTIM2_GPCM_TCH(0xf) | \
 190                                         FTIM2_GPCM_TWP(0x3E))
 191 #define CONFIG_SYS_CS3_FTIM3            0x0
 192
 193 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
 194 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 195 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 196 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 197 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 198 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 199 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 200 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 201 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 202 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 203 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 204 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 205 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 206 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 207 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 208 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 209 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 210 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 211
 212 #define CONFIG_SPL_PAD_TO               0x80000
 213 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (1024 * 1024)
 214 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 215 #else
 216 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 217 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 218 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 219 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 220 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 221 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 222 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 223 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 224 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 225 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 226 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 227 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 228 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 229 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 230 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 231 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 232 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 233 #endif
 234
 235 /* Debug Server firmware */
 236 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 237 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 238 #endif
 239 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 240
 241 #ifdef CONFIG_TARGET_LS2081ARDB
 242 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 243 #define QIXIS_QMAP_MASK                 0x07
 244 #define QIXIS_QMAP_SHIFT                5
 245 #define QIXIS_LBMAP_DFLTBANK            0x00
 246 #define QIXIS_LBMAP_QSPI                0x00
 247 #define QIXIS_RCW_SRC_QSPI              0x62
 248 #define QIXIS_LBMAP_ALTBANK             0x20
 249 #define QIXIS_RST_CTL_RESET             0x31
 250 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 251 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 252 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 253 #define QIXIS_LBMAP_MASK                0x0f
 254 #define QIXIS_RST_CTL_RESET_EN          0x30
 255 #endif
 256
 257 /*
 258  * I2C
 259  */
 260 #ifdef CONFIG_TARGET_LS2081ARDB
 261 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 262 #endif
 263 #define I2C_MUX_PCA_ADDR                0x75
 264 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 265
 266 /* I2C bus multiplexer */
 267 #define I2C_MUX_CH_DEFAULT      0x8
 268
 269 /* SPI */
 270 #if defined(CONFIG_FSL_DSPI)
 271 #define CONFIG_SPI_FLASH_STMICRO
 272 #endif
 273
 274 /*
 275  * RTC configuration
 276  */
 277 #define RTC
 278 #ifdef CONFIG_TARGET_LS2081ARDB
 279 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 280 #else
 281 #define CONFIG_RTC_DS3231               1
 282 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 283 #endif
 284
 285 /* EEPROM */
 286 #define CONFIG_SYS_I2C_EEPROM_NXID
 287 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 288
 289 #define CONFIG_FSL_MEMAC
 290
 291 #ifdef CONFIG_PCI
 292 #define CONFIG_PCI_SCAN_SHOW
 293 #endif
 294
 295 #define BOOT_TARGET_DEVICES(func) \
 296         func(USB, usb, 0) \
 297         func(MMC, mmc, 0) \
 298         func(SCSI, scsi, 0) \
 299         func(DHCP, dhcp, na)
 300 #include <config_distro_bootcmd.h>
 301
 302 #ifdef CONFIG_TFABOOT
 303 #define QSPI_MC_INIT_CMD                                \
 304         "sf probe 0:0; "                                \
 305         "sf read 0x80640000 0x640000 0x80000; "         \
 306         "env exists secureboot && "                     \
 307         "esbc_validate 0x80640000 && "                  \
 308         "esbc_validate 0x80680000; "                    \
 309         "sf read 0x80a00000 0xa00000 0x200000; "        \
 310         "sf read 0x80e00000 0xe00000 0x100000; "        \
 311         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 312 #define SD_MC_INIT_CMD                          \
 313         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 314         "mmc read 0x80e00000 0x7000 0x800;"     \
 315         "env exists secureboot && "             \
 316         "mmc read 0x80640000 0x3200 0x20 && "   \
 317         "mmc read 0x80680000 0x3400 0x20 && "   \
 318         "esbc_validate 0x80640000 && "          \
 319         "esbc_validate 0x80680000 ;"            \
 320         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 321 #define IFC_MC_INIT_CMD                         \
 322         "env exists secureboot && "     \
 323         "esbc_validate 0x580640000 && "         \
 324         "esbc_validate 0x580680000; "           \
 325         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 326 #else
 327 #ifdef CONFIG_QSPI_BOOT
 328 #define MC_INIT_CMD                                     \
 329         "mcinitcmd=sf probe 0:0; "                      \
 330         "sf read 0x80640000 0x640000 0x80000; "         \
 331         "env exists secureboot && "                     \
 332         "esbc_validate 0x80640000 && "                  \
 333         "esbc_validate 0x80680000; "                    \
 334         "sf read 0x80a00000 0xa00000 0x200000; "        \
 335         "sf read 0x80e00000 0xe00000 0x100000; "        \
 336         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 337 #elif defined(CONFIG_SD_BOOT)
 338 #define MC_INIT_CMD                             \
 339         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 340         "mmc read 0x80e00000 0x7000 0x800;"     \
 341         "env exists secureboot && "             \
 342         "mmc read 0x80640000 0x3200 0x20 && "   \
 343         "mmc read 0x80680000 0x3400 0x20 && "   \
 344         "esbc_validate 0x80640000 && "          \
 345         "esbc_validate 0x80680000 ;"            \
 346         "fsl_mc start mc 0x80a00000 0x80e00000\0" \
 347         "mcmemsize=0x70000000\0"
 348 #else
 349 #define MC_INIT_CMD                             \
 350         "mcinitcmd=env exists secureboot && "   \
 351         "esbc_validate 0x580640000 && "         \
 352         "esbc_validate 0x580680000; "           \
 353         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 354 #endif
 355 #endif
 356
 357 /* Initial environment variables */
 358 #undef CONFIG_EXTRA_ENV_SETTINGS
 359 #ifdef CONFIG_TFABOOT
 360 #define CONFIG_EXTRA_ENV_SETTINGS               \
 361         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 362         "ramdisk_addr=0x800000\0"               \
 363         "ramdisk_size=0x2000000\0"              \
 364         "fdt_high=0xa0000000\0"                 \
 365         "initrd_high=0xffffffffffffffff\0"      \
 366         "fdt_addr=0x64f00000\0"                 \
 367         "kernel_addr=0x581000000\0"             \
 368         "kernel_start=0x1000000\0"              \
 369         "kernelheader_start=0x800000\0"         \
 370         "scriptaddr=0x80000000\0"               \
 371         "scripthdraddr=0x80080000\0"            \
 372         "fdtheader_addr_r=0x80100000\0"         \
 373         "kernelheader_addr_r=0x80200000\0"      \
 374         "kernelheader_addr=0x580600000\0"       \
 375         "kernel_addr_r=0x81000000\0"            \
 376         "kernelheader_size=0x40000\0"           \
 377         "fdt_addr_r=0x90000000\0"               \
 378         "load_addr=0xa0000000\0"                \
 379         "kernel_size=0x2800000\0"               \
 380         "kernel_addr_sd=0x8000\0"               \
 381         "kernel_size_sd=0x14000\0"              \
 382         "console=ttyAMA0,38400n8\0"             \
 383         "mcmemsize=0x70000000\0"                \
 384         "sd_bootcmd=echo Trying load from SD ..;" \
 385         "mmcinfo; mmc read $load_addr "         \
 386         "$kernel_addr_sd $kernel_size_sd && "   \
 387         "bootm $load_addr#$board\0"             \
 388         QSPI_MC_INIT_CMD                                \
 389         BOOTENV                                 \
 390         "boot_scripts=ls2088ardb_boot.scr\0"    \
 391         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 392         "scan_dev_for_boot_part="               \
 393                 "part list ${devtype} ${devnum} devplist; "     \
 394                 "env exists devplist || setenv devplist 1; "    \
 395                 "for distro_bootpart in ${devplist}; do "       \
 396                         "if fstype ${devtype} "                 \
 397                                 "${devnum}:${distro_bootpart} " \
 398                                 "bootfstype; then "             \
 399                                 "run scan_dev_for_boot; "       \
 400                         "fi; "                                  \
 401                 "done\0"                                        \
 402         "boot_a_script="                                        \
 403                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 404                         "${scriptaddr} ${prefix}${script}; "    \
 405                 "env exists secureboot && load ${devtype} "     \
 406                         "${devnum}:${distro_bootpart} "         \
 407                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 408                         "&& esbc_validate ${scripthdraddr};"    \
 409                 "source ${scriptaddr}\0"                        \
 410         "qspi_bootcmd=echo Trying load from qspi..;"            \
 411                 "sf probe && sf read $load_addr "               \
 412                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 413                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 414                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 415                 " bootm $load_addr#$board\0"                    \
 416         "nor_bootcmd=echo Trying load from nor..;"              \
 417                 "cp.b $kernel_addr $load_addr "                 \
 418                 "$kernel_size ; env exists secureboot && "      \
 419                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 420                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 421                 "bootm $load_addr#$board\0"
 422 #else
 423 #define CONFIG_EXTRA_ENV_SETTINGS               \
 424         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 425         "ramdisk_addr=0x800000\0"               \
 426         "ramdisk_size=0x2000000\0"              \
 427         "fdt_high=0xa0000000\0"                 \
 428         "initrd_high=0xffffffffffffffff\0"      \
 429         "fdt_addr=0x64f00000\0"                 \
 430         "kernel_addr=0x581000000\0"             \
 431         "kernel_start=0x1000000\0"              \
 432         "kernelheader_start=0x600000\0"         \
 433         "scriptaddr=0x80000000\0"               \
 434         "scripthdraddr=0x80080000\0"            \
 435         "fdtheader_addr_r=0x80100000\0"         \
 436         "kernelheader_addr_r=0x80200000\0"      \
 437         "kernelheader_addr=0x580600000\0"       \
 438         "kernel_addr_r=0x81000000\0"            \
 439         "kernelheader_size=0x40000\0"           \
 440         "fdt_addr_r=0x90000000\0"               \
 441         "load_addr=0xa0000000\0"                \
 442         "kernel_size=0x2800000\0"               \
 443         "kernel_addr_sd=0x8000\0"               \
 444         "kernel_size_sd=0x14000\0"              \
 445         "console=ttyAMA0,38400n8\0"             \
 446         "mcmemsize=0x70000000\0"                \
 447         "sd_bootcmd=echo Trying load from SD ..;" \
 448         "mmcinfo; mmc read $load_addr "         \
 449         "$kernel_addr_sd $kernel_size_sd && "   \
 450         "bootm $load_addr#$board\0"             \
 451         MC_INIT_CMD                             \
 452         BOOTENV                                 \
 453         "boot_scripts=ls2088ardb_boot.scr\0"    \
 454         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 455         "scan_dev_for_boot_part="               \
 456                 "part list ${devtype} ${devnum} devplist; "     \
 457                 "env exists devplist || setenv devplist 1; "    \
 458                 "for distro_bootpart in ${devplist}; do "       \
 459                         "if fstype ${devtype} "                 \
 460                                 "${devnum}:${distro_bootpart} " \
 461                                 "bootfstype; then "             \
 462                                 "run scan_dev_for_boot; "       \
 463                         "fi; "                                  \
 464                 "done\0"                                        \
 465         "boot_a_script="                                        \
 466                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 467                         "${scriptaddr} ${prefix}${script}; "    \
 468                 "env exists secureboot && load ${devtype} "     \
 469                         "${devnum}:${distro_bootpart} "         \
 470                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 471                         "env exists secureboot "        \
 472                         "&& esbc_validate ${scripthdraddr};"    \
 473                 "source ${scriptaddr}\0"                        \
 474         "qspi_bootcmd=echo Trying load from qspi..;"            \
 475                 "sf probe && sf read $load_addr "               \
 476                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 477                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 478                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 479                 " bootm $load_addr#$board\0"                    \
 480         "nor_bootcmd=echo Trying load from nor..;"              \
 481                 "cp.b $kernel_addr $load_addr "                 \
 482                 "$kernel_size ; env exists secureboot && "      \
 483                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 484                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 485                 "bootm $load_addr#$board\0"
 486 #endif
 487
 488 #ifdef CONFIG_TFABOOT
 489 #define QSPI_NOR_BOOTCOMMAND                                            \
 490                         "sf probe 0:0; "                                \
 491                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 492                         "env exists mcinitcmd && env exists secureboot "\
 493                         "&& esbc_validate 0x806c0000; "                 \
 494                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 495                         "env exists mcinitcmd && "                      \
 496                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 497                         "run distro_bootcmd;run qspi_bootcmd; "         \
 498                         "env exists secureboot && esbc_halt;"
 499
 500 /* Try to boot an on-SD kernel first, then do normal distro boot */
 501 #define SD_BOOTCOMMAND                                          \
 502                         "env exists mcinitcmd && env exists secureboot "\
 503                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 504                         "&& esbc_validate $load_addr; "                 \
 505                         "env exists mcinitcmd && run mcinitcmd "        \
 506                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 507                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 508                         "run distro_bootcmd;run sd_bootcmd; "           \
 509                         "env exists secureboot && esbc_halt;"
 510
 511 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 512 #define IFC_NOR_BOOTCOMMAND                                             \
 513                         "env exists mcinitcmd && env exists secureboot "\
 514                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 515                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 516                         "run distro_bootcmd;run nor_bootcmd; "          \
 517                         "env exists secureboot && esbc_halt;"
 518 #else
 519 #undef CONFIG_BOOTCOMMAND
 520 #ifdef CONFIG_QSPI_BOOT
 521 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 522 #define CONFIG_BOOTCOMMAND                                              \
 523                         "sf probe 0:0; "                                \
 524                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 525                         "env exists mcinitcmd && env exists secureboot "\
 526                         "&& esbc_validate 0x806C0000; "                 \
 527                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 528                         "env exists mcinitcmd && "                      \
 529                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 530                         "run distro_bootcmd;run qspi_bootcmd; "         \
 531                         "env exists secureboot && esbc_halt;"
 532 #elif defined(CONFIG_SD_BOOT)
 533 /* Try to boot an on-SD kernel first, then do normal distro boot */
 534 #define CONFIG_BOOTCOMMAND                                              \
 535                         "env exists mcinitcmd && env exists secureboot "\
 536                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 537                         "&& esbc_validate $load_addr; "                 \
 538                         "env exists mcinitcmd && run mcinitcmd "        \
 539                         "&& mmc read 0x88000000 0x6800 0x800 "          \
 540                         "&& fsl_mc lazyapply dpl 0x88000000; "          \
 541                         "run distro_bootcmd;run sd_bootcmd; "           \
 542                         "env exists secureboot && esbc_halt;"
 543 #else
 544 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 545 #define CONFIG_BOOTCOMMAND                                              \
 546                         "env exists mcinitcmd && env exists secureboot "\
 547                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 548                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 549                         "run distro_bootcmd;run nor_bootcmd; "          \
 550                         "env exists secureboot && esbc_halt;"
 551 #endif
 552 #endif
 553
 554 /* MAC/PHY configuration */
 555 #define CORTINA_PHY_ADDR1       0x10
 556 #define CORTINA_PHY_ADDR2       0x11
 557 #define CORTINA_PHY_ADDR3       0x12
 558 #define CORTINA_PHY_ADDR4       0x13
 559 #define AQ_PHY_ADDR1            0x00
 560 #define AQ_PHY_ADDR2            0x01
 561 #define AQ_PHY_ADDR3            0x02
 562 #define AQ_PHY_ADDR4            0x03
 563 #define AQR405_IRQ_MASK         0x36
 564 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 565
 566 #include <asm/fsl_secure_boot.h>
 567
 568 #endif /* __LS2_RDB_H */