1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #ifdef CONFIG_FSL_QSPI
13 #ifdef CONFIG_TARGET_LS2081ARDB
14 #define CONFIG_QIXIS_I2C_ACCESS
18 #define I2C_MUX_CH_VOL_MONITOR 0xa
19 #define I2C_VOL_MONITOR_ADDR 0x38
20 #define CONFIG_VOL_MONITOR_IR36021_READ
21 #define CONFIG_VOL_MONITOR_IR36021_SET
23 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
24 #ifndef CONFIG_SPL_BUILD
27 /* step the IR regulator in 5mV increments */
28 #define IR_VDD_STEP_DOWN 5
29 #define IR_VDD_STEP_UP 5
30 /* The lowest and highest voltage allowed for LS2080ARDB */
31 #define VDD_MV_MIN 819
32 #define VDD_MV_MAX 1212
35 unsigned long get_board_sys_clk(void);
38 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
39 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
41 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
42 #define SPD_EEPROM_ADDRESS1 0x51
43 #define SPD_EEPROM_ADDRESS2 0x52
44 #define SPD_EEPROM_ADDRESS3 0x53
45 #define SPD_EEPROM_ADDRESS4 0x54
46 #define SPD_EEPROM_ADDRESS5 0x55
47 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
48 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
49 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
50 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
51 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
52 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
53 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
57 #define CONFIG_SCSI_AHCI_PLAT
59 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
60 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
62 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
63 #define CONFIG_SYS_SCSI_MAX_LUN 1
64 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
65 CONFIG_SYS_SCSI_MAX_LUN)
67 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
69 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
70 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
71 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
73 #define CONFIG_SYS_NOR0_CSPR \
74 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
78 #define CONFIG_SYS_NOR0_CSPR_EARLY \
79 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
83 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
84 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
85 FTIM0_NOR_TEADC(0x5) | \
87 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
88 FTIM1_NOR_TRAD_NOR(0x1a) |\
89 FTIM1_NOR_TSEQRAD_NOR(0x13))
90 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
91 FTIM2_NOR_TCH(0x4) | \
92 FTIM2_NOR_TWPH(0x0E) | \
94 #define CONFIG_SYS_NOR_FTIM3 0x04000000
95 #define CONFIG_SYS_IFC_CCR 0x01000000
97 #ifdef CONFIG_MTD_NOR_FLASH
98 #define CONFIG_SYS_FLASH_QUIET_TEST
99 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
101 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
102 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
103 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
104 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
106 #define CONFIG_SYS_FLASH_EMPTY_INFO
107 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
108 CONFIG_SYS_FLASH_BASE + 0x40000000}
111 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
112 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
114 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
115 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
116 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
117 | CSPR_MSEL_NAND /* MSEL = NAND */ \
119 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
121 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
122 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
123 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
124 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
125 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
126 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
127 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
129 /* ONFI NAND Flash mode0 Timing Params */
130 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
131 FTIM0_NAND_TWP(0x30) | \
132 FTIM0_NAND_TWCHT(0x0e) | \
133 FTIM0_NAND_TWH(0x14))
134 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
135 FTIM1_NAND_TWBE(0xab) | \
136 FTIM1_NAND_TRR(0x1c) | \
137 FTIM1_NAND_TRP(0x30))
138 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
139 FTIM2_NAND_TREH(0x14) | \
140 FTIM2_NAND_TWHRE(0x3c))
141 #define CONFIG_SYS_NAND_FTIM3 0x0
143 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
144 #define CONFIG_SYS_MAX_NAND_DEVICE 1
145 #define CONFIG_MTD_NAND_VERIFY_WRITE
147 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
148 #define QIXIS_LBMAP_SWITCH 0x06
149 #define QIXIS_LBMAP_MASK 0x0f
150 #define QIXIS_LBMAP_SHIFT 0
151 #define QIXIS_LBMAP_DFLTBANK 0x00
152 #define QIXIS_LBMAP_ALTBANK 0x04
153 #define QIXIS_LBMAP_NAND 0x09
154 #define QIXIS_RST_CTL_RESET 0x31
155 #define QIXIS_RST_CTL_RESET_EN 0x30
156 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
157 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
158 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
159 #define QIXIS_RCW_SRC_NAND 0x119
160 #define QIXIS_RST_FORCE_MEM 0x01
162 #define CONFIG_SYS_CSPR3_EXT (0x0)
163 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
167 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
172 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
173 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
174 /* QIXIS Timing parameters for IFC CS3 */
175 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
176 FTIM0_GPCM_TEADC(0x0e) | \
177 FTIM0_GPCM_TEAHC(0x0e))
178 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
179 FTIM1_GPCM_TRAD(0x3f))
180 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
181 FTIM2_GPCM_TCH(0xf) | \
182 FTIM2_GPCM_TWP(0x3E))
183 #define CONFIG_SYS_CS3_FTIM3 0x0
185 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
186 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
187 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
188 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
189 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
190 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
191 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
192 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
193 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
194 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
195 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
196 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
197 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
198 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
199 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
200 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
201 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
202 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
204 #define CONFIG_SPL_PAD_TO 0x80000
205 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
207 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
208 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
209 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
210 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
211 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
212 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
213 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
214 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
215 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
216 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
217 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
218 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
219 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
220 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
221 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
222 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
223 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
226 /* Debug Server firmware */
227 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
228 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
230 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
232 #ifdef CONFIG_TARGET_LS2081ARDB
233 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
234 #define QIXIS_QMAP_MASK 0x07
235 #define QIXIS_QMAP_SHIFT 5
236 #define QIXIS_LBMAP_DFLTBANK 0x00
237 #define QIXIS_LBMAP_QSPI 0x00
238 #define QIXIS_RCW_SRC_QSPI 0x62
239 #define QIXIS_LBMAP_ALTBANK 0x20
240 #define QIXIS_RST_CTL_RESET 0x31
241 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
242 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
243 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
244 #define QIXIS_LBMAP_MASK 0x0f
245 #define QIXIS_RST_CTL_RESET_EN 0x30
251 #ifdef CONFIG_TARGET_LS2081ARDB
252 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
254 #define I2C_MUX_PCA_ADDR 0x75
255 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
257 /* I2C bus multiplexer */
258 #define I2C_MUX_CH_DEFAULT 0x8
261 #if defined(CONFIG_FSL_DSPI)
262 #define CONFIG_SPI_FLASH_STMICRO
269 #ifdef CONFIG_TARGET_LS2081ARDB
270 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
272 #define CONFIG_RTC_DS3231 1
273 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
277 #define CONFIG_SYS_I2C_EEPROM_NXID
278 #define CONFIG_SYS_EEPROM_BUS_NUM 0
280 #define CONFIG_FSL_MEMAC
283 #define CONFIG_PCI_SCAN_SHOW
286 #define BOOT_TARGET_DEVICES(func) \
289 func(SCSI, scsi, 0) \
291 #include <config_distro_bootcmd.h>
293 #ifdef CONFIG_TFABOOT
294 #define QSPI_MC_INIT_CMD \
296 "sf read 0x80640000 0x640000 0x80000; " \
297 "env exists secureboot && " \
298 "esbc_validate 0x80640000 && " \
299 "esbc_validate 0x80680000; " \
300 "sf read 0x80a00000 0xa00000 0x200000; " \
301 "sf read 0x80e00000 0xe00000 0x100000; " \
302 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
303 #define SD_MC_INIT_CMD \
304 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
305 "mmc read 0x80e00000 0x7000 0x800;" \
306 "env exists secureboot && " \
307 "mmc read 0x80640000 0x3200 0x20 && " \
308 "mmc read 0x80680000 0x3400 0x20 && " \
309 "esbc_validate 0x80640000 && " \
310 "esbc_validate 0x80680000 ;" \
311 "fsl_mc start mc 0x80a00000 0x80e00000\0"
312 #define IFC_MC_INIT_CMD \
313 "env exists secureboot && " \
314 "esbc_validate 0x580640000 && " \
315 "esbc_validate 0x580680000; " \
316 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
318 #ifdef CONFIG_QSPI_BOOT
319 #define MC_INIT_CMD \
320 "mcinitcmd=sf probe 0:0; " \
321 "sf read 0x80640000 0x640000 0x80000; " \
322 "env exists secureboot && " \
323 "esbc_validate 0x80640000 && " \
324 "esbc_validate 0x80680000; " \
325 "sf read 0x80a00000 0xa00000 0x200000; " \
326 "sf read 0x80e00000 0xe00000 0x100000; " \
327 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
328 #elif defined(CONFIG_SD_BOOT)
329 #define MC_INIT_CMD \
330 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
331 "mmc read 0x80e00000 0x7000 0x800;" \
332 "env exists secureboot && " \
333 "mmc read 0x80640000 0x3200 0x20 && " \
334 "mmc read 0x80680000 0x3400 0x20 && " \
335 "esbc_validate 0x80640000 && " \
336 "esbc_validate 0x80680000 ;" \
337 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
338 "mcmemsize=0x70000000\0"
340 #define MC_INIT_CMD \
341 "mcinitcmd=env exists secureboot && " \
342 "esbc_validate 0x580640000 && " \
343 "esbc_validate 0x580680000; " \
344 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
348 /* Initial environment variables */
349 #undef CONFIG_EXTRA_ENV_SETTINGS
350 #ifdef CONFIG_TFABOOT
351 #define CONFIG_EXTRA_ENV_SETTINGS \
352 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
353 "ramdisk_addr=0x800000\0" \
354 "ramdisk_size=0x2000000\0" \
355 "fdt_high=0xa0000000\0" \
356 "initrd_high=0xffffffffffffffff\0" \
357 "fdt_addr=0x64f00000\0" \
358 "kernel_addr=0x581000000\0" \
359 "kernel_start=0x1000000\0" \
360 "kernelheader_start=0x800000\0" \
361 "scriptaddr=0x80000000\0" \
362 "scripthdraddr=0x80080000\0" \
363 "fdtheader_addr_r=0x80100000\0" \
364 "kernelheader_addr_r=0x80200000\0" \
365 "kernelheader_addr=0x580600000\0" \
366 "kernel_addr_r=0x81000000\0" \
367 "kernelheader_size=0x40000\0" \
368 "fdt_addr_r=0x90000000\0" \
369 "load_addr=0xa0000000\0" \
370 "kernel_size=0x2800000\0" \
371 "kernel_addr_sd=0x8000\0" \
372 "kernel_size_sd=0x14000\0" \
373 "console=ttyAMA0,38400n8\0" \
374 "mcmemsize=0x70000000\0" \
375 "sd_bootcmd=echo Trying load from SD ..;" \
376 "mmcinfo; mmc read $load_addr " \
377 "$kernel_addr_sd $kernel_size_sd && " \
378 "bootm $load_addr#$board\0" \
381 "boot_scripts=ls2088ardb_boot.scr\0" \
382 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
383 "scan_dev_for_boot_part=" \
384 "part list ${devtype} ${devnum} devplist; " \
385 "env exists devplist || setenv devplist 1; " \
386 "for distro_bootpart in ${devplist}; do " \
387 "if fstype ${devtype} " \
388 "${devnum}:${distro_bootpart} " \
389 "bootfstype; then " \
390 "run scan_dev_for_boot; " \
394 "load ${devtype} ${devnum}:${distro_bootpart} " \
395 "${scriptaddr} ${prefix}${script}; " \
396 "env exists secureboot && load ${devtype} " \
397 "${devnum}:${distro_bootpart} " \
398 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
399 "&& esbc_validate ${scripthdraddr};" \
400 "source ${scriptaddr}\0" \
401 "qspi_bootcmd=echo Trying load from qspi..;" \
402 "sf probe && sf read $load_addr " \
403 "$kernel_start $kernel_size ; env exists secureboot &&" \
404 "sf read $kernelheader_addr_r $kernelheader_start " \
405 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
406 " bootm $load_addr#$board\0" \
407 "nor_bootcmd=echo Trying load from nor..;" \
408 "cp.b $kernel_addr $load_addr " \
409 "$kernel_size ; env exists secureboot && " \
410 "cp.b $kernelheader_addr $kernelheader_addr_r " \
411 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
412 "bootm $load_addr#$board\0"
414 #define CONFIG_EXTRA_ENV_SETTINGS \
415 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
416 "ramdisk_addr=0x800000\0" \
417 "ramdisk_size=0x2000000\0" \
418 "fdt_high=0xa0000000\0" \
419 "initrd_high=0xffffffffffffffff\0" \
420 "fdt_addr=0x64f00000\0" \
421 "kernel_addr=0x581000000\0" \
422 "kernel_start=0x1000000\0" \
423 "kernelheader_start=0x600000\0" \
424 "scriptaddr=0x80000000\0" \
425 "scripthdraddr=0x80080000\0" \
426 "fdtheader_addr_r=0x80100000\0" \
427 "kernelheader_addr_r=0x80200000\0" \
428 "kernelheader_addr=0x580600000\0" \
429 "kernel_addr_r=0x81000000\0" \
430 "kernelheader_size=0x40000\0" \
431 "fdt_addr_r=0x90000000\0" \
432 "load_addr=0xa0000000\0" \
433 "kernel_size=0x2800000\0" \
434 "kernel_addr_sd=0x8000\0" \
435 "kernel_size_sd=0x14000\0" \
436 "console=ttyAMA0,38400n8\0" \
437 "mcmemsize=0x70000000\0" \
438 "sd_bootcmd=echo Trying load from SD ..;" \
439 "mmcinfo; mmc read $load_addr " \
440 "$kernel_addr_sd $kernel_size_sd && " \
441 "bootm $load_addr#$board\0" \
444 "boot_scripts=ls2088ardb_boot.scr\0" \
445 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
446 "scan_dev_for_boot_part=" \
447 "part list ${devtype} ${devnum} devplist; " \
448 "env exists devplist || setenv devplist 1; " \
449 "for distro_bootpart in ${devplist}; do " \
450 "if fstype ${devtype} " \
451 "${devnum}:${distro_bootpart} " \
452 "bootfstype; then " \
453 "run scan_dev_for_boot; " \
457 "load ${devtype} ${devnum}:${distro_bootpart} " \
458 "${scriptaddr} ${prefix}${script}; " \
459 "env exists secureboot && load ${devtype} " \
460 "${devnum}:${distro_bootpart} " \
461 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
462 "env exists secureboot " \
463 "&& esbc_validate ${scripthdraddr};" \
464 "source ${scriptaddr}\0" \
465 "qspi_bootcmd=echo Trying load from qspi..;" \
466 "sf probe && sf read $load_addr " \
467 "$kernel_start $kernel_size ; env exists secureboot &&" \
468 "sf read $kernelheader_addr_r $kernelheader_start " \
469 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
470 " bootm $load_addr#$board\0" \
471 "nor_bootcmd=echo Trying load from nor..;" \
472 "cp.b $kernel_addr $load_addr " \
473 "$kernel_size ; env exists secureboot && " \
474 "cp.b $kernelheader_addr $kernelheader_addr_r " \
475 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
476 "bootm $load_addr#$board\0"
479 #ifdef CONFIG_TFABOOT
480 #define QSPI_NOR_BOOTCOMMAND \
482 "sf read 0x806c0000 0x6c0000 0x40000; " \
483 "env exists mcinitcmd && env exists secureboot "\
484 "&& esbc_validate 0x806c0000; " \
485 "sf read 0x80d00000 0xd00000 0x100000; " \
486 "env exists mcinitcmd && " \
487 "fsl_mc lazyapply dpl 0x80d00000; " \
488 "run distro_bootcmd;run qspi_bootcmd; " \
489 "env exists secureboot && esbc_halt;"
491 /* Try to boot an on-SD kernel first, then do normal distro boot */
492 #define SD_BOOTCOMMAND \
493 "env exists mcinitcmd && env exists secureboot "\
494 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
495 "&& esbc_validate $load_addr; " \
496 "env exists mcinitcmd && run mcinitcmd " \
497 "&& mmc read 0x80d00000 0x6800 0x800 " \
498 "&& fsl_mc lazyapply dpl 0x80d00000; " \
499 "run distro_bootcmd;run sd_bootcmd; " \
500 "env exists secureboot && esbc_halt;"
502 /* Try to boot an on-NOR kernel first, then do normal distro boot */
503 #define IFC_NOR_BOOTCOMMAND \
504 "env exists mcinitcmd && env exists secureboot "\
505 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
506 "&& fsl_mc lazyapply dpl 0x580d00000;" \
507 "run distro_bootcmd;run nor_bootcmd; " \
508 "env exists secureboot && esbc_halt;"
510 #ifdef CONFIG_QSPI_BOOT
511 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
512 #elif defined(CONFIG_SD_BOOT)
513 /* Try to boot an on-SD kernel first, then do normal distro boot */
515 /* Try to boot an on-NOR kernel first, then do normal distro boot */
519 /* MAC/PHY configuration */
520 #define CORTINA_PHY_ADDR1 0x10
521 #define CORTINA_PHY_ADDR2 0x11
522 #define CORTINA_PHY_ADDR3 0x12
523 #define CORTINA_PHY_ADDR4 0x13
524 #define AQ_PHY_ADDR1 0x00
525 #define AQ_PHY_ADDR2 0x01
526 #define AQ_PHY_ADDR3 0x02
527 #define AQ_PHY_ADDR4 0x03
528 #define AQR405_IRQ_MASK 0x36
529 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
531 #include <asm/fsl_secure_boot.h>
533 #endif /* __LS2_RDB_H */