include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #ifdef CONFIG_TARGET_LS2081ARDB
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16 #define CONFIG_SYS_I2C_EARLY_INIT
  17 #endif
  18
  19 #define I2C_MUX_CH_VOL_MONITOR          0xa
  20 #define I2C_VOL_MONITOR_ADDR            0x38
  21 #define CONFIG_VOL_MONITOR_IR36021_READ
  22 #define CONFIG_VOL_MONITOR_IR36021_SET
  23
  24 #define CONFIG_VID_FLS_ENV              "ls2080ardb_vdd_mv"
  25 #ifndef CONFIG_SPL_BUILD
  26 #define CONFIG_VID
  27 #endif
  28 /* step the IR regulator in 5mV increments */
  29 #define IR_VDD_STEP_DOWN                5
  30 #define IR_VDD_STEP_UP                  5
  31 /* The lowest and highest voltage allowed for LS2080ARDB */
  32 #define VDD_MV_MIN                      819
  33 #define VDD_MV_MAX                      1212
  34
  35 #ifndef __ASSEMBLY__
  36 unsigned long get_board_sys_clk(void);
  37 #endif
  38
  39 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  40 #define CONFIG_DDR_CLK_FREQ             133333333
  41 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  42
  43 #define CONFIG_DDR_SPD
  44 #define CONFIG_DDR_ECC
  45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  46 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  47 #define SPD_EEPROM_ADDRESS1     0x51
  48 #define SPD_EEPROM_ADDRESS2     0x52
  49 #define SPD_EEPROM_ADDRESS3     0x53
  50 #define SPD_EEPROM_ADDRESS4     0x54
  51 #define SPD_EEPROM_ADDRESS5     0x55
  52 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  53 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  54 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  55 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  56 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  57 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  58 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  59 #endif
  60 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  61
  62 /* SATA */
  63 #define CONFIG_SCSI_AHCI_PLAT
  64
  65 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  66 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  67
  68 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  69 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  70 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  71                                                 CONFIG_SYS_SCSI_MAX_LUN)
  72 #ifdef CONFIG_TFABOOT
  73 #define CONFIG_SYS_MMC_ENV_DEV         0
  74
  75 #define CONFIG_ENV_SIZE                 0x2000
  76 #define CONFIG_ENV_OFFSET               0x500000        /* 5MB */
  77 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + \
  78                                          CONFIG_ENV_OFFSET)
  79 #define CONFIG_ENV_SECT_SIZE            0x40000
  80 #endif
  81
  82 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  83 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
  84
  85 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  86 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  87 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  88
  89 #define CONFIG_SYS_NOR0_CSPR                                    \
  90         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  91         CSPR_PORT_SIZE_16                                       | \
  92         CSPR_MSEL_NOR                                           | \
  93         CSPR_V)
  94 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  95         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  96         CSPR_PORT_SIZE_16                                       | \
  97         CSPR_MSEL_NOR                                           | \
  98         CSPR_V)
  99 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
 100 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 101                                 FTIM0_NOR_TEADC(0x5) | \
 102                                 FTIM0_NOR_TEAHC(0x5))
 103 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 104                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
 105                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 106 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 107                                 FTIM2_NOR_TCH(0x4) | \
 108                                 FTIM2_NOR_TWPH(0x0E) | \
 109                                 FTIM2_NOR_TWP(0x1c))
 110 #define CONFIG_SYS_NOR_FTIM3    0x04000000
 111 #define CONFIG_SYS_IFC_CCR      0x01000000
 112
 113 #ifdef CONFIG_MTD_NOR_FLASH
 114 #define CONFIG_SYS_FLASH_QUIET_TEST
 115 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 116
 117 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 118 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 119 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 120 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 121
 122 #define CONFIG_SYS_FLASH_EMPTY_INFO
 123 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 124                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 125 #endif
 126
 127 #define CONFIG_NAND_FSL_IFC
 128 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 129 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 130
 131 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 132 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 133                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 134                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 135                                 | CSPR_V)
 136 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 137
 138 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 139                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 140                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 141                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 142                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 143                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 144                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 145
 146 #define CONFIG_SYS_NAND_ONFI_DETECTION
 147
 148 /* ONFI NAND Flash mode0 Timing Params */
 149 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 150                                         FTIM0_NAND_TWP(0x30)   | \
 151                                         FTIM0_NAND_TWCHT(0x0e) | \
 152                                         FTIM0_NAND_TWH(0x14))
 153 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 154                                         FTIM1_NAND_TWBE(0xab)  | \
 155                                         FTIM1_NAND_TRR(0x1c)   | \
 156                                         FTIM1_NAND_TRP(0x30))
 157 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 158                                         FTIM2_NAND_TREH(0x14) | \
 159                                         FTIM2_NAND_TWHRE(0x3c))
 160 #define CONFIG_SYS_NAND_FTIM3           0x0
 161
 162 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 163 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 164 #define CONFIG_MTD_NAND_VERIFY_WRITE
 165
 166 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 167 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 168 #define QIXIS_LBMAP_SWITCH              0x06
 169 #define QIXIS_LBMAP_MASK                0x0f
 170 #define QIXIS_LBMAP_SHIFT               0
 171 #define QIXIS_LBMAP_DFLTBANK            0x00
 172 #define QIXIS_LBMAP_ALTBANK             0x04
 173 #define QIXIS_LBMAP_NAND                0x09
 174 #define QIXIS_RST_CTL_RESET             0x31
 175 #define QIXIS_RST_CTL_RESET_EN          0x30
 176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 177 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 179 #define QIXIS_RCW_SRC_NAND              0x119
 180 #define QIXIS_RST_FORCE_MEM             0x01
 181
 182 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 183 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 184                                 | CSPR_PORT_SIZE_8 \
 185                                 | CSPR_MSEL_GPCM \
 186                                 | CSPR_V)
 187 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 188                                 | CSPR_PORT_SIZE_8 \
 189                                 | CSPR_MSEL_GPCM \
 190                                 | CSPR_V)
 191
 192 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 193 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 194 /* QIXIS Timing parameters for IFC CS3 */
 195 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 196                                         FTIM0_GPCM_TEADC(0x0e) | \
 197                                         FTIM0_GPCM_TEAHC(0x0e))
 198 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 199                                         FTIM1_GPCM_TRAD(0x3f))
 200 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 201                                         FTIM2_GPCM_TCH(0xf) | \
 202                                         FTIM2_GPCM_TWP(0x3E))
 203 #define CONFIG_SYS_CS3_FTIM3            0x0
 204
 205 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
 206 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 207 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 208 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 209 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 210 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 211 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 212 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 213 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 214 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 215 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 216 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 217 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 218 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 219 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 220 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 221 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 222 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 223
 224 #ifndef CONFIG_TFABOOT
 225 #define CONFIG_ENV_OFFSET               (2048 * 1024)
 226 #define CONFIG_ENV_SECT_SIZE            0x20000
 227 #define CONFIG_ENV_SIZE                 0x2000
 228 #endif
 229 #define CONFIG_SPL_PAD_TO               0x80000
 230 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (1024 * 1024)
 231 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 232 #else
 233 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 234 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 235 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 236 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 237 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 238 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 239 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 240 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 241 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 242 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 243 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 244 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 245 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 246 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 247 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 248 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 249 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 250
 251 #ifndef CONFIG_TFABOOT
 252 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 253 #define CONFIG_ENV_SECT_SIZE            0x20000
 254 #define CONFIG_ENV_SIZE                 0x2000
 255 #endif
 256 #endif
 257
 258 /* Debug Server firmware */
 259 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 260 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 261 #endif
 262 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 263
 264 #ifdef CONFIG_TARGET_LS2081ARDB
 265 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 266 #define QIXIS_QMAP_MASK                 0x07
 267 #define QIXIS_QMAP_SHIFT                5
 268 #define QIXIS_LBMAP_DFLTBANK            0x00
 269 #define QIXIS_LBMAP_QSPI                0x00
 270 #define QIXIS_RCW_SRC_QSPI              0x62
 271 #define QIXIS_LBMAP_ALTBANK             0x20
 272 #define QIXIS_RST_CTL_RESET             0x31
 273 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 274 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 275 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 276 #define QIXIS_LBMAP_MASK                0x0f
 277 #define QIXIS_RST_CTL_RESET_EN          0x30
 278 #endif
 279
 280 /*
 281  * I2C
 282  */
 283 #ifdef CONFIG_TARGET_LS2081ARDB
 284 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 285 #endif
 286 #define I2C_MUX_PCA_ADDR                0x75
 287 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 288
 289 /* I2C bus multiplexer */
 290 #define I2C_MUX_CH_DEFAULT      0x8
 291
 292 /* SPI */
 293 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 294 #ifdef CONFIG_FSL_DSPI
 295 #define CONFIG_SPI_FLASH_STMICRO
 296 #endif
 297 #define FSL_QSPI_FLASH_SIZE             SZ_64M  /* 64MB */
 298 #define FSL_QSPI_FLASH_NUM              2
 299 #endif
 300
 301 /*
 302  * RTC configuration
 303  */
 304 #define RTC
 305 #ifdef CONFIG_TARGET_LS2081ARDB
 306 #define CONFIG_RTC_PCF8563              1
 307 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 308 #else
 309 #define CONFIG_RTC_DS3231               1
 310 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 311 #endif
 312
 313 /* EEPROM */
 314 #define CONFIG_ID_EEPROM
 315 #define CONFIG_SYS_I2C_EEPROM_NXID
 316 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 317 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 318 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 319 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 320 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 321
 322 #define CONFIG_FSL_MEMAC
 323
 324 #ifdef CONFIG_PCI
 325 #define CONFIG_PCI_SCAN_SHOW
 326 #endif
 327
 328 /*  MMC  */
 329 #ifdef CONFIG_MMC
 330 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 331 #endif
 332
 333 #define BOOT_TARGET_DEVICES(func) \
 334         func(USB, usb, 0) \
 335         func(MMC, mmc, 0) \
 336         func(SCSI, scsi, 0)
 337 #include <config_distro_bootcmd.h>
 338
 339 #ifdef CONFIG_TFABOOT
 340 #define QSPI_MC_INIT_CMD                        \
 341         "env exists secureboot && "             \
 342         "esbc_validate 0x20700000 && "          \
 343         "esbc_validate 0x20740000;"             \
 344         "fsl_mc start mc 0x20a00000 0x20e00000 \0"
 345 #define SD_MC_INIT_CMD                          \
 346         "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
 347         "mmc read 0x80100000 0x7000 0x800;"     \
 348         "env exists secureboot && "             \
 349         "mmc read 0x80700000 0x3800 0x10 && "   \
 350         "mmc read 0x80740000 0x3A00 0x10 && "   \
 351         "esbc_validate 0x80700000 && "          \
 352         "esbc_validate 0x80740000 ;"            \
 353         "fsl_mc start mc 0x80000000 0x80100000\0"
 354 #define IFC_MC_INIT_CMD                         \
 355         "env exists secureboot && "     \
 356         "esbc_validate 0x580700000 && "         \
 357         "esbc_validate 0x580740000; "           \
 358         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 359 #else
 360 #ifdef CONFIG_QSPI_BOOT
 361 #define MC_INIT_CMD                             \
 362         "mcinitcmd=env exists secureboot && "   \
 363         "esbc_validate 0x20700000 && "          \
 364         "esbc_validate 0x20740000;"             \
 365         "fsl_mc start mc 0x20a00000 0x20e00000 \0"
 366 #elif defined(CONFIG_SD_BOOT)
 367 #define MC_INIT_CMD                             \
 368         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
 369         "mmc read 0x80100000 0x7000 0x800;"     \
 370         "env exists secureboot && "             \
 371         "mmc read 0x80700000 0x3800 0x10 && "   \
 372         "mmc read 0x80740000 0x3A00 0x10 && "   \
 373         "esbc_validate 0x80700000 && "          \
 374         "esbc_validate 0x80740000 ;"            \
 375         "fsl_mc start mc 0x80000000 0x80100000\0" \
 376         "mcmemsize=0x70000000\0"
 377 #else
 378 #define MC_INIT_CMD                             \
 379         "mcinitcmd=env exists secureboot && "   \
 380         "esbc_validate 0x580700000 && "         \
 381         "esbc_validate 0x580740000; "           \
 382         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 383 #endif
 384 #endif
 385
 386 /* Initial environment variables */
 387 #undef CONFIG_EXTRA_ENV_SETTINGS
 388 #ifdef CONFIG_TFABOOT
 389 #define CONFIG_EXTRA_ENV_SETTINGS               \
 390         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 391         "ramdisk_addr=0x800000\0"               \
 392         "ramdisk_size=0x2000000\0"              \
 393         "fdt_high=0xa0000000\0"                 \
 394         "initrd_high=0xffffffffffffffff\0"      \
 395         "fdt_addr=0x64f00000\0"                 \
 396         "kernel_addr=0x581000000\0"             \
 397         "kernel_start=0x1000000\0"              \
 398         "kernelheader_start=0x800000\0"         \
 399         "scriptaddr=0x80000000\0"               \
 400         "scripthdraddr=0x80080000\0"            \
 401         "fdtheader_addr_r=0x80100000\0"         \
 402         "kernelheader_addr_r=0x80200000\0"      \
 403         "kernelheader_addr=0x580800000\0"       \
 404         "kernel_addr_r=0x81000000\0"            \
 405         "kernelheader_size=0x40000\0"           \
 406         "fdt_addr_r=0x90000000\0"               \
 407         "load_addr=0xa0000000\0"                \
 408         "kernel_size=0x2800000\0"               \
 409         "kernel_addr_sd=0x8000\0"               \
 410         "kernel_size_sd=0x14000\0"              \
 411         "console=ttyAMA0,38400n8\0"             \
 412         "mcmemsize=0x70000000\0"                \
 413         "sd_bootcmd=echo Trying load from SD ..;" \
 414         "mmcinfo; mmc read $load_addr "         \
 415         "$kernel_addr_sd $kernel_size_sd && "   \
 416         "bootm $load_addr#$board\0"             \
 417         QSPI_MC_INIT_CMD                                \
 418         BOOTENV                                 \
 419         "boot_scripts=ls2088ardb_boot.scr\0"    \
 420         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 421         "scan_dev_for_boot_part="               \
 422                 "part list ${devtype} ${devnum} devplist; "     \
 423                 "env exists devplist || setenv devplist 1; "    \
 424                 "for distro_bootpart in ${devplist}; do "       \
 425                         "if fstype ${devtype} "                 \
 426                                 "${devnum}:${distro_bootpart} " \
 427                                 "bootfstype; then "             \
 428                                 "run scan_dev_for_boot; "       \
 429                         "fi; "                                  \
 430                 "done\0"                                        \
 431         "scan_dev_for_boot="                                    \
 432                 "echo Scanning ${devtype} "                     \
 433                         "${devnum}:${distro_bootpart}...; "     \
 434                 "for prefix in ${boot_prefixes}; do "           \
 435                         "run scan_dev_for_scripts; "            \
 436                 "done;\0"                                       \
 437         "boot_a_script="                                        \
 438                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 439                         "${scriptaddr} ${prefix}${script}; "    \
 440                 "env exists secureboot && load ${devtype} "     \
 441                         "${devnum}:${distro_bootpart} "         \
 442                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 443                         "&& esbc_validate ${scripthdraddr};"    \
 444                 "source ${scriptaddr}\0"                        \
 445         "qspi_bootcmd=echo Trying load from qspi..;"            \
 446                 "sf probe && sf read $load_addr "               \
 447                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 448                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 449                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 450                 " bootm $load_addr#$board\0"                    \
 451         "nor_bootcmd=echo Trying load from nor..;"              \
 452                 "cp.b $kernel_addr $load_addr "                 \
 453                 "$kernel_size ; env exists secureboot && "      \
 454                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 455                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 456                 "bootm $load_addr#$board\0"
 457 #else
 458 #define CONFIG_EXTRA_ENV_SETTINGS               \
 459         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 460         "ramdisk_addr=0x800000\0"               \
 461         "ramdisk_size=0x2000000\0"              \
 462         "fdt_high=0xa0000000\0"                 \
 463         "initrd_high=0xffffffffffffffff\0"      \
 464         "fdt_addr=0x64f00000\0"                 \
 465         "kernel_addr=0x581000000\0"             \
 466         "kernel_start=0x1000000\0"              \
 467         "kernelheader_start=0x800000\0"         \
 468         "scriptaddr=0x80000000\0"               \
 469         "scripthdraddr=0x80080000\0"            \
 470         "fdtheader_addr_r=0x80100000\0"         \
 471         "kernelheader_addr_r=0x80200000\0"      \
 472         "kernelheader_addr=0x580800000\0"       \
 473         "kernel_addr_r=0x81000000\0"            \
 474         "kernelheader_size=0x40000\0"           \
 475         "fdt_addr_r=0x90000000\0"               \
 476         "load_addr=0xa0000000\0"                \
 477         "kernel_size=0x2800000\0"               \
 478         "kernel_addr_sd=0x8000\0"               \
 479         "kernel_size_sd=0x14000\0"              \
 480         "console=ttyAMA0,38400n8\0"             \
 481         "mcmemsize=0x70000000\0"                \
 482         "sd_bootcmd=echo Trying load from SD ..;" \
 483         "mmcinfo; mmc read $load_addr "         \
 484         "$kernel_addr_sd $kernel_size_sd && "   \
 485         "bootm $load_addr#$board\0"             \
 486         MC_INIT_CMD                             \
 487         BOOTENV                                 \
 488         "boot_scripts=ls2088ardb_boot.scr\0"    \
 489         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 490         "scan_dev_for_boot_part="               \
 491                 "part list ${devtype} ${devnum} devplist; "     \
 492                 "env exists devplist || setenv devplist 1; "    \
 493                 "for distro_bootpart in ${devplist}; do "       \
 494                         "if fstype ${devtype} "                 \
 495                                 "${devnum}:${distro_bootpart} " \
 496                                 "bootfstype; then "             \
 497                                 "run scan_dev_for_boot; "       \
 498                         "fi; "                                  \
 499                 "done\0"                                        \
 500         "scan_dev_for_boot="                                    \
 501                 "echo Scanning ${devtype} "                     \
 502                         "${devnum}:${distro_bootpart}...; "     \
 503                 "for prefix in ${boot_prefixes}; do "           \
 504                         "run scan_dev_for_scripts; "            \
 505                 "done;\0"                                       \
 506         "boot_a_script="                                        \
 507                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 508                         "${scriptaddr} ${prefix}${script}; "    \
 509                 "env exists secureboot && load ${devtype} "     \
 510                         "${devnum}:${distro_bootpart} "         \
 511                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 512                         "&& esbc_validate ${scripthdraddr};"    \
 513                 "source ${scriptaddr}\0"                        \
 514         "qspi_bootcmd=echo Trying load from qspi..;"            \
 515                 "sf probe && sf read $load_addr "               \
 516                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 517                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 518                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 519                 " bootm $load_addr#$board\0"                    \
 520         "nor_bootcmd=echo Trying load from nor..;"              \
 521                 "cp.b $kernel_addr $load_addr "                 \
 522                 "$kernel_size ; env exists secureboot && "      \
 523                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 524                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 525                 "bootm $load_addr#$board\0"
 526 #endif
 527
 528 #ifdef CONFIG_TFABOOT
 529 #define QSPI_NOR_BOOTCOMMAND                                            \
 530                         "env exists mcinitcmd && env exists secureboot "\
 531                         "&& esbc_validate 0x20780000; "                 \
 532                         "env exists mcinitcmd && "                      \
 533                         "fsl_mc lazyapply dpl 0x20d00000; "             \
 534                         "run distro_bootcmd;run qspi_bootcmd; "         \
 535                         "env exists secureboot && esbc_halt;"
 536
 537 /* Try to boot an on-SD kernel first, then do normal distro boot */
 538 #define SD_BOOTCOMMAND                                          \
 539                         "env exists mcinitcmd && env exists secureboot "\
 540                         "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
 541                         "&& esbc_validate $load_addr; "                 \
 542                         "env exists mcinitcmd && run mcinitcmd "        \
 543                         "&& mmc read 0x88000000 0x6800 0x800 "          \
 544                         "&& fsl_mc lazyapply dpl 0x88000000; "          \
 545                         "run distro_bootcmd;run sd_bootcmd; "           \
 546                         "env exists secureboot && esbc_halt;"
 547
 548 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 549 #define IFC_NOR_BOOTCOMMAND                                             \
 550                         "env exists mcinitcmd && env exists secureboot "\
 551                         "&& esbc_validate 0x580780000; env exists mcinitcmd "\
 552                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 553                         "run distro_bootcmd;run nor_bootcmd; "          \
 554                         "env exists secureboot && esbc_halt;"
 555 #else
 556 #undef CONFIG_BOOTCOMMAND
 557 #ifdef CONFIG_QSPI_BOOT
 558 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 559 #define CONFIG_BOOTCOMMAND                                              \
 560                         "env exists mcinitcmd && env exists secureboot "\
 561                         "&& esbc_validate 0x20780000; "                 \
 562                         "env exists mcinitcmd && "                      \
 563                         "fsl_mc lazyapply dpl 0x20d00000; "             \
 564                         "run distro_bootcmd;run qspi_bootcmd; "         \
 565                         "env exists secureboot && esbc_halt;"
 566 #elif defined(CONFIG_SD_BOOT)
 567 /* Try to boot an on-SD kernel first, then do normal distro boot */
 568 #define CONFIG_BOOTCOMMAND                                              \
 569                         "env exists mcinitcmd && env exists secureboot "\
 570                         "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
 571                         "&& esbc_validate $load_addr; "                 \
 572                         "env exists mcinitcmd && run mcinitcmd "        \
 573                         "&& mmc read 0x88000000 0x6800 0x800 "          \
 574                         "&& fsl_mc lazyapply dpl 0x88000000; "          \
 575                         "run distro_bootcmd;run sd_bootcmd; "           \
 576                         "env exists secureboot && esbc_halt;"
 577 #else
 578 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 579 #define CONFIG_BOOTCOMMAND                                              \
 580                         "env exists mcinitcmd && env exists secureboot "\
 581                         "&& esbc_validate 0x580780000; env exists mcinitcmd "\
 582                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 583                         "run distro_bootcmd;run nor_bootcmd; "          \
 584                         "env exists secureboot && esbc_halt;"
 585 #endif
 586 #endif
 587
 588 /* MAC/PHY configuration */
 589 #ifdef CONFIG_FSL_MC_ENET
 590 #define CONFIG_PHY_CORTINA
 591 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 592 #ifdef CONFIG_QSPI_BOOT
 593 #define CONFIG_CORTINA_FW_ADDR          0x20980000
 594 #else
 595 #define CONFIG_CORTINA_FW_ADDR          0x580980000
 596 #endif
 597 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 598
 599 #define CORTINA_PHY_ADDR1       0x10
 600 #define CORTINA_PHY_ADDR2       0x11
 601 #define CORTINA_PHY_ADDR3       0x12
 602 #define CORTINA_PHY_ADDR4       0x13
 603 #define AQ_PHY_ADDR1            0x00
 604 #define AQ_PHY_ADDR2            0x01
 605 #define AQ_PHY_ADDR3            0x02
 606 #define AQ_PHY_ADDR4            0x03
 607 #define AQR405_IRQ_MASK         0x36
 608
 609 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 610 #endif
 611
 612 #include <asm/fsl_secure_boot.h>
 613
 614 #endif /* __LS2_RDB_H */