include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #define I2C_MUX_CH_VOL_MONITOR          0xa
  13 #define I2C_VOL_MONITOR_ADDR            0x38
  14
  15 /* step the IR regulator in 5mV increments */
  16 #define IR_VDD_STEP_DOWN                5
  17 #define IR_VDD_STEP_UP                  5
  18 /* The lowest and highest voltage allowed for LS2080ARDB */
  19 #define VDD_MV_MIN                      819
  20 #define VDD_MV_MAX                      1212
  21
  22 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  23
  24 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  25 #define SPD_EEPROM_ADDRESS1     0x51
  26 #define SPD_EEPROM_ADDRESS2     0x52
  27 #define SPD_EEPROM_ADDRESS3     0x53
  28 #define SPD_EEPROM_ADDRESS4     0x54
  29 #define SPD_EEPROM_ADDRESS5     0x55
  30 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  31 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  32
  33 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  34
  35 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  36 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  37 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  38
  39 #define CONFIG_SYS_NOR0_CSPR                                    \
  40         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  41         CSPR_PORT_SIZE_16                                       | \
  42         CSPR_MSEL_NOR                                           | \
  43         CSPR_V)
  44 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  45         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  46         CSPR_PORT_SIZE_16                                       | \
  47         CSPR_MSEL_NOR                                           | \
  48         CSPR_V)
  49 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  50 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  51                                 FTIM0_NOR_TEADC(0x5) | \
  52                                 FTIM0_NOR_TEAHC(0x5))
  53 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  54                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  55                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  56 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  57                                 FTIM2_NOR_TCH(0x4) | \
  58                                 FTIM2_NOR_TWPH(0x0E) | \
  59                                 FTIM2_NOR_TWP(0x1c))
  60 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  61 #define CONFIG_SYS_IFC_CCR      0x01000000
  62
  63 #ifdef CONFIG_MTD_NOR_FLASH
  64 #define CONFIG_SYS_FLASH_QUIET_TEST
  65 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  66
  67 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  68                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  69 #endif
  70
  71 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  72 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  73
  74 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  75 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  76                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  77                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  78                                 | CSPR_V)
  79 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  80
  81 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  82                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  83                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  84                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  85                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
  86                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
  87                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
  88
  89 /* ONFI NAND Flash mode0 Timing Params */
  90 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
  91                                         FTIM0_NAND_TWP(0x30)   | \
  92                                         FTIM0_NAND_TWCHT(0x0e) | \
  93                                         FTIM0_NAND_TWH(0x14))
  94 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
  95                                         FTIM1_NAND_TWBE(0xab)  | \
  96                                         FTIM1_NAND_TRR(0x1c)   | \
  97                                         FTIM1_NAND_TRP(0x30))
  98 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
  99                                         FTIM2_NAND_TREH(0x14) | \
 100                                         FTIM2_NAND_TWHRE(0x3c))
 101 #define CONFIG_SYS_NAND_FTIM3           0x0
 102
 103 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 104 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 105 #define CONFIG_MTD_NAND_VERIFY_WRITE
 106
 107 #define QIXIS_LBMAP_SWITCH              0x06
 108 #define QIXIS_LBMAP_MASK                0x0f
 109 #define QIXIS_LBMAP_SHIFT               0
 110 #define QIXIS_LBMAP_DFLTBANK            0x00
 111 #define QIXIS_LBMAP_ALTBANK             0x04
 112 #define QIXIS_LBMAP_NAND                0x09
 113 #define QIXIS_RST_CTL_RESET             0x31
 114 #define QIXIS_RST_CTL_RESET_EN          0x30
 115 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 116 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 117 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 118 #define QIXIS_RCW_SRC_NAND              0x119
 119 #define QIXIS_RST_FORCE_MEM             0x01
 120
 121 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 122 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 123                                 | CSPR_PORT_SIZE_8 \
 124                                 | CSPR_MSEL_GPCM \
 125                                 | CSPR_V)
 126 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 127                                 | CSPR_PORT_SIZE_8 \
 128                                 | CSPR_MSEL_GPCM \
 129                                 | CSPR_V)
 130
 131 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 132 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 133 /* QIXIS Timing parameters for IFC CS3 */
 134 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 135                                         FTIM0_GPCM_TEADC(0x0e) | \
 136                                         FTIM0_GPCM_TEAHC(0x0e))
 137 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 138                                         FTIM1_GPCM_TRAD(0x3f))
 139 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 140                                         FTIM2_GPCM_TCH(0xf) | \
 141                                         FTIM2_GPCM_TWP(0x3E))
 142 #define CONFIG_SYS_CS3_FTIM3            0x0
 143
 144 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
 145 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 146 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 147 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 148 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 149 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 150 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 151 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 152 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 153 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 154 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 155 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 156 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 157 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 158 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 159 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 160 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 161 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 162
 163 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 164 #else
 165 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 166 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 167 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 168 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 169 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 170 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 171 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 172 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 173 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 174 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 175 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 176 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 177 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 178 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 179 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 180 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 181 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 182 #endif
 183
 184 /* Debug Server firmware */
 185 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 186 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 187 #endif
 188 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 189
 190 #ifdef CONFIG_TARGET_LS2081ARDB
 191 #define QIXIS_QMAP_MASK                 0x07
 192 #define QIXIS_QMAP_SHIFT                5
 193 #define QIXIS_LBMAP_DFLTBANK            0x00
 194 #define QIXIS_LBMAP_QSPI                0x00
 195 #define QIXIS_RCW_SRC_QSPI              0x62
 196 #define QIXIS_LBMAP_ALTBANK             0x20
 197 #define QIXIS_RST_CTL_RESET             0x31
 198 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 199 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 200 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 201 #define QIXIS_LBMAP_MASK                0x0f
 202 #define QIXIS_RST_CTL_RESET_EN          0x30
 203 #endif
 204
 205 /*
 206  * I2C
 207  */
 208 #ifdef CONFIG_TARGET_LS2081ARDB
 209 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 210 #endif
 211 #define I2C_MUX_PCA_ADDR                0x75
 212 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 213
 214 /* I2C bus multiplexer */
 215 #define I2C_MUX_CH_DEFAULT      0x8
 216
 217 /* SPI */
 218
 219 /*
 220  * RTC configuration
 221  */
 222 #define RTC
 223 #ifdef CONFIG_TARGET_LS2081ARDB
 224 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 225 #else
 226 #define CONFIG_RTC_DS3231               1
 227 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 228 #endif
 229
 230 /* EEPROM */
 231 #define CONFIG_SYS_I2C_EEPROM_NXID
 232 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 233
 234 #define CONFIG_FSL_MEMAC
 235
 236 #define BOOT_TARGET_DEVICES(func) \
 237         func(USB, usb, 0) \
 238         func(MMC, mmc, 0) \
 239         func(SCSI, scsi, 0) \
 240         func(DHCP, dhcp, na)
 241 #include <config_distro_bootcmd.h>
 242
 243 #ifdef CONFIG_TFABOOT
 244 #define QSPI_MC_INIT_CMD                                \
 245         "sf probe 0:0; "                                \
 246         "sf read 0x80640000 0x640000 0x80000; "         \
 247         "env exists secureboot && "                     \
 248         "esbc_validate 0x80640000 && "                  \
 249         "esbc_validate 0x80680000; "                    \
 250         "sf read 0x80a00000 0xa00000 0x200000; "        \
 251         "sf read 0x80e00000 0xe00000 0x100000; "        \
 252         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 253 #define SD_MC_INIT_CMD                          \
 254         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 255         "mmc read 0x80e00000 0x7000 0x800;"     \
 256         "env exists secureboot && "             \
 257         "mmc read 0x80640000 0x3200 0x20 && "   \
 258         "mmc read 0x80680000 0x3400 0x20 && "   \
 259         "esbc_validate 0x80640000 && "          \
 260         "esbc_validate 0x80680000 ;"            \
 261         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 262 #define IFC_MC_INIT_CMD                         \
 263         "env exists secureboot && "     \
 264         "esbc_validate 0x580640000 && "         \
 265         "esbc_validate 0x580680000; "           \
 266         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 267 #else
 268 #ifdef CONFIG_QSPI_BOOT
 269 #define MC_INIT_CMD                                     \
 270         "mcinitcmd=sf probe 0:0; "                      \
 271         "sf read 0x80640000 0x640000 0x80000; "         \
 272         "env exists secureboot && "                     \
 273         "esbc_validate 0x80640000 && "                  \
 274         "esbc_validate 0x80680000; "                    \
 275         "sf read 0x80a00000 0xa00000 0x200000; "        \
 276         "sf read 0x80e00000 0xe00000 0x100000; "        \
 277         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 278 #elif defined(CONFIG_SD_BOOT)
 279 #define MC_INIT_CMD                             \
 280         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 281         "mmc read 0x80e00000 0x7000 0x800;"     \
 282         "env exists secureboot && "             \
 283         "mmc read 0x80640000 0x3200 0x20 && "   \
 284         "mmc read 0x80680000 0x3400 0x20 && "   \
 285         "esbc_validate 0x80640000 && "          \
 286         "esbc_validate 0x80680000 ;"            \
 287         "fsl_mc start mc 0x80a00000 0x80e00000\0" \
 288         "mcmemsize=0x70000000\0"
 289 #else
 290 #define MC_INIT_CMD                             \
 291         "mcinitcmd=env exists secureboot && "   \
 292         "esbc_validate 0x580640000 && "         \
 293         "esbc_validate 0x580680000; "           \
 294         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 295 #endif
 296 #endif
 297
 298 /* Initial environment variables */
 299 #undef CONFIG_EXTRA_ENV_SETTINGS
 300 #ifdef CONFIG_TFABOOT
 301 #define CONFIG_EXTRA_ENV_SETTINGS               \
 302         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 303         "ramdisk_addr=0x800000\0"               \
 304         "ramdisk_size=0x2000000\0"              \
 305         "fdt_high=0xa0000000\0"                 \
 306         "initrd_high=0xffffffffffffffff\0"      \
 307         "kernel_addr=0x581000000\0"             \
 308         "kernel_start=0x1000000\0"              \
 309         "kernelheader_start=0x800000\0"         \
 310         "scriptaddr=0x80000000\0"               \
 311         "scripthdraddr=0x80080000\0"            \
 312         "fdtheader_addr_r=0x80100000\0"         \
 313         "kernelheader_addr_r=0x80200000\0"      \
 314         "kernelheader_addr=0x580600000\0"       \
 315         "kernel_addr_r=0x81000000\0"            \
 316         "kernelheader_size=0x40000\0"           \
 317         "fdt_addr_r=0x90000000\0"               \
 318         "load_addr=0xa0000000\0"                \
 319         "kernel_size=0x2800000\0"               \
 320         "kernel_addr_sd=0x8000\0"               \
 321         "kernel_size_sd=0x14000\0"              \
 322         "console=ttyAMA0,38400n8\0"             \
 323         "mcmemsize=0x70000000\0"                \
 324         "sd_bootcmd=echo Trying load from SD ..;" \
 325         "mmcinfo; mmc read $load_addr "         \
 326         "$kernel_addr_sd $kernel_size_sd && "   \
 327         "bootm $load_addr#$board\0"             \
 328         QSPI_MC_INIT_CMD                                \
 329         BOOTENV                                 \
 330         "boot_scripts=ls2088ardb_boot.scr\0"    \
 331         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 332         "scan_dev_for_boot_part="               \
 333                 "part list ${devtype} ${devnum} devplist; "     \
 334                 "env exists devplist || setenv devplist 1; "    \
 335                 "for distro_bootpart in ${devplist}; do "       \
 336                         "if fstype ${devtype} "                 \
 337                                 "${devnum}:${distro_bootpart} " \
 338                                 "bootfstype; then "             \
 339                                 "run scan_dev_for_boot; "       \
 340                         "fi; "                                  \
 341                 "done\0"                                        \
 342         "boot_a_script="                                        \
 343                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 344                         "${scriptaddr} ${prefix}${script}; "    \
 345                 "env exists secureboot && load ${devtype} "     \
 346                         "${devnum}:${distro_bootpart} "         \
 347                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 348                         "&& esbc_validate ${scripthdraddr};"    \
 349                 "source ${scriptaddr}\0"                        \
 350         "qspi_bootcmd=echo Trying load from qspi..;"            \
 351                 "sf probe && sf read $load_addr "               \
 352                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 353                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 354                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 355                 " bootm $load_addr#$board\0"                    \
 356         "nor_bootcmd=echo Trying load from nor..;"              \
 357                 "cp.b $kernel_addr $load_addr "                 \
 358                 "$kernel_size ; env exists secureboot && "      \
 359                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 360                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 361                 "bootm $load_addr#$board\0"
 362 #else
 363 #define CONFIG_EXTRA_ENV_SETTINGS               \
 364         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 365         "ramdisk_addr=0x800000\0"               \
 366         "ramdisk_size=0x2000000\0"              \
 367         "fdt_high=0xa0000000\0"                 \
 368         "initrd_high=0xffffffffffffffff\0"      \
 369         "kernel_addr=0x581000000\0"             \
 370         "kernel_start=0x1000000\0"              \
 371         "kernelheader_start=0x600000\0"         \
 372         "scriptaddr=0x80000000\0"               \
 373         "scripthdraddr=0x80080000\0"            \
 374         "fdtheader_addr_r=0x80100000\0"         \
 375         "kernelheader_addr_r=0x80200000\0"      \
 376         "kernelheader_addr=0x580600000\0"       \
 377         "kernel_addr_r=0x81000000\0"            \
 378         "kernelheader_size=0x40000\0"           \
 379         "fdt_addr_r=0x90000000\0"               \
 380         "load_addr=0xa0000000\0"                \
 381         "kernel_size=0x2800000\0"               \
 382         "kernel_addr_sd=0x8000\0"               \
 383         "kernel_size_sd=0x14000\0"              \
 384         "console=ttyAMA0,38400n8\0"             \
 385         "mcmemsize=0x70000000\0"                \
 386         "sd_bootcmd=echo Trying load from SD ..;" \
 387         "mmcinfo; mmc read $load_addr "         \
 388         "$kernel_addr_sd $kernel_size_sd && "   \
 389         "bootm $load_addr#$board\0"             \
 390         MC_INIT_CMD                             \
 391         BOOTENV                                 \
 392         "boot_scripts=ls2088ardb_boot.scr\0"    \
 393         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 394         "scan_dev_for_boot_part="               \
 395                 "part list ${devtype} ${devnum} devplist; "     \
 396                 "env exists devplist || setenv devplist 1; "    \
 397                 "for distro_bootpart in ${devplist}; do "       \
 398                         "if fstype ${devtype} "                 \
 399                                 "${devnum}:${distro_bootpart} " \
 400                                 "bootfstype; then "             \
 401                                 "run scan_dev_for_boot; "       \
 402                         "fi; "                                  \
 403                 "done\0"                                        \
 404         "boot_a_script="                                        \
 405                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 406                         "${scriptaddr} ${prefix}${script}; "    \
 407                 "env exists secureboot && load ${devtype} "     \
 408                         "${devnum}:${distro_bootpart} "         \
 409                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 410                         "env exists secureboot "        \
 411                         "&& esbc_validate ${scripthdraddr};"    \
 412                 "source ${scriptaddr}\0"                        \
 413         "qspi_bootcmd=echo Trying load from qspi..;"            \
 414                 "sf probe && sf read $load_addr "               \
 415                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 416                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 417                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 418                 " bootm $load_addr#$board\0"                    \
 419         "nor_bootcmd=echo Trying load from nor..;"              \
 420                 "cp.b $kernel_addr $load_addr "                 \
 421                 "$kernel_size ; env exists secureboot && "      \
 422                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 423                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 424                 "bootm $load_addr#$board\0"
 425 #endif
 426
 427 #ifdef CONFIG_TFABOOT
 428 #define QSPI_NOR_BOOTCOMMAND                                            \
 429                         "sf probe 0:0; "                                \
 430                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 431                         "env exists mcinitcmd && env exists secureboot "\
 432                         "&& esbc_validate 0x806c0000; "                 \
 433                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 434                         "env exists mcinitcmd && "                      \
 435                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 436                         "run distro_bootcmd;run qspi_bootcmd; "         \
 437                         "env exists secureboot && esbc_halt;"
 438
 439 /* Try to boot an on-SD kernel first, then do normal distro boot */
 440 #define SD_BOOTCOMMAND                                          \
 441                         "env exists mcinitcmd && env exists secureboot "\
 442                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 443                         "&& esbc_validate $load_addr; "                 \
 444                         "env exists mcinitcmd && run mcinitcmd "        \
 445                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 446                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 447                         "run distro_bootcmd;run sd_bootcmd; "           \
 448                         "env exists secureboot && esbc_halt;"
 449
 450 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 451 #define IFC_NOR_BOOTCOMMAND                                             \
 452                         "env exists mcinitcmd && env exists secureboot "\
 453                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 454                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 455                         "run distro_bootcmd;run nor_bootcmd; "          \
 456                         "env exists secureboot && esbc_halt;"
 457 #else
 458 #ifdef CONFIG_QSPI_BOOT
 459 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 460 #elif defined(CONFIG_SD_BOOT)
 461 /* Try to boot an on-SD kernel first, then do normal distro boot */
 462 #else
 463 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 464 #endif
 465 #endif
 466
 467 /* MAC/PHY configuration */
 468 #define CORTINA_PHY_ADDR1       0x10
 469 #define CORTINA_PHY_ADDR2       0x11
 470 #define CORTINA_PHY_ADDR3       0x12
 471 #define CORTINA_PHY_ADDR4       0x13
 472 #define AQ_PHY_ADDR1            0x00
 473 #define AQ_PHY_ADDR2            0x01
 474 #define AQ_PHY_ADDR3            0x02
 475 #define AQ_PHY_ADDR4            0x03
 476 #define AQR405_IRQ_MASK         0x36
 477
 478 #include <asm/fsl_secure_boot.h>
 479
 480 #endif /* __LS2_RDB_H */