include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #define I2C_MUX_CH_VOL_MONITOR          0xa
  13 #define I2C_VOL_MONITOR_ADDR            0x38
  14
  15 /* step the IR regulator in 5mV increments */
  16 #define IR_VDD_STEP_DOWN                5
  17 #define IR_VDD_STEP_UP                  5
  18 /* The lowest and highest voltage allowed for LS2080ARDB */
  19 #define VDD_MV_MIN                      819
  20 #define VDD_MV_MAX                      1212
  21
  22 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  23
  24 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  25 #define SPD_EEPROM_ADDRESS1     0x51
  26 #define SPD_EEPROM_ADDRESS2     0x52
  27 #define SPD_EEPROM_ADDRESS3     0x53
  28 #define SPD_EEPROM_ADDRESS4     0x54
  29 #define SPD_EEPROM_ADDRESS5     0x55
  30 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  31 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  32
  33 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  34
  35 #define CFG_SYS_NOR0_CSPR_EXT   (0x0)
  36 #define CFG_SYS_NOR_AMASK               IFC_AMASK(128*1024*1024)
  37 #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  38
  39 #define CFG_SYS_NOR0_CSPR                                       \
  40         (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)                | \
  41         CSPR_PORT_SIZE_16                                       | \
  42         CSPR_MSEL_NOR                                           | \
  43         CSPR_V)
  44 #define CFG_SYS_NOR0_CSPR_EARLY                         \
  45         (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY)  | \
  46         CSPR_PORT_SIZE_16                                       | \
  47         CSPR_MSEL_NOR                                           | \
  48         CSPR_V)
  49 #define CFG_SYS_NOR_CSOR        CSOR_NOR_ADM_SHIFT(12)
  50 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
  51                                 FTIM0_NOR_TEADC(0x5) | \
  52                                 FTIM0_NOR_TEAHC(0x5))
  53 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
  54                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  55                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  56 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
  57                                 FTIM2_NOR_TCH(0x4) | \
  58                                 FTIM2_NOR_TWPH(0x0E) | \
  59                                 FTIM2_NOR_TWP(0x1c))
  60 #define CFG_SYS_NOR_FTIM3       0x04000000
  61 #define CFG_SYS_IFC_CCR 0x01000000
  62
  63 #ifdef CONFIG_MTD_NOR_FLASH
  64 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  65
  66 #define CFG_SYS_FLASH_BANKS_LIST        { CFG_SYS_FLASH_BASE,\
  67                                          CFG_SYS_FLASH_BASE + 0x40000000}
  68 #endif
  69
  70 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  71 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
  72                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  73                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  74                                 | CSPR_V)
  75 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64 * 1024)
  76
  77 #define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  78                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  79                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  80                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  81                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
  82                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
  83                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
  84
  85 /* ONFI NAND Flash mode0 Timing Params */
  86 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x0e) | \
  87                                         FTIM0_NAND_TWP(0x30)   | \
  88                                         FTIM0_NAND_TWCHT(0x0e) | \
  89                                         FTIM0_NAND_TWH(0x14))
  90 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x64) | \
  91                                         FTIM1_NAND_TWBE(0xab)  | \
  92                                         FTIM1_NAND_TRR(0x1c)   | \
  93                                         FTIM1_NAND_TRP(0x30))
  94 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x1e) | \
  95                                         FTIM2_NAND_TREH(0x14) | \
  96                                         FTIM2_NAND_TWHRE(0x3c))
  97 #define CFG_SYS_NAND_FTIM3              0x0
  98
  99 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 100 #define CONFIG_MTD_NAND_VERIFY_WRITE
 101
 102 #define QIXIS_LBMAP_SWITCH              0x06
 103 #define QIXIS_LBMAP_MASK                0x0f
 104 #define QIXIS_LBMAP_SHIFT               0
 105 #define QIXIS_LBMAP_DFLTBANK            0x00
 106 #define QIXIS_LBMAP_ALTBANK             0x04
 107 #define QIXIS_LBMAP_NAND                0x09
 108 #define QIXIS_RST_CTL_RESET             0x31
 109 #define QIXIS_RST_CTL_RESET_EN          0x30
 110 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 111 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 112 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 113 #define QIXIS_RCW_SRC_NAND              0x119
 114 #define QIXIS_RST_FORCE_MEM             0x01
 115
 116 #define CFG_SYS_CSPR3_EXT       (0x0)
 117 #define CFG_SYS_CSPR3   (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 118                                 | CSPR_PORT_SIZE_8 \
 119                                 | CSPR_MSEL_GPCM \
 120                                 | CSPR_V)
 121 #define CFG_SYS_CSPR3_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 122                                 | CSPR_PORT_SIZE_8 \
 123                                 | CSPR_MSEL_GPCM \
 124                                 | CSPR_V)
 125
 126 #define CFG_SYS_AMASK3  IFC_AMASK(64*1024)
 127 #define CFG_SYS_CSOR3   CSOR_GPCM_ADM_SHIFT(12)
 128 /* QIXIS Timing parameters for IFC CS3 */
 129 #define CFG_SYS_CS3_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 130                                         FTIM0_GPCM_TEADC(0x0e) | \
 131                                         FTIM0_GPCM_TEAHC(0x0e))
 132 #define CFG_SYS_CS3_FTIM1               (FTIM1_GPCM_TACO(0xff) | \
 133                                         FTIM1_GPCM_TRAD(0x3f))
 134 #define CFG_SYS_CS3_FTIM2               (FTIM2_GPCM_TCS(0xf) | \
 135                                         FTIM2_GPCM_TCH(0xf) | \
 136                                         FTIM2_GPCM_TWP(0x3E))
 137 #define CFG_SYS_CS3_FTIM3               0x0
 138
 139 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
 140 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NOR0_CSPR_EXT
 141 #define CFG_SYS_CSPR2           CFG_SYS_NOR0_CSPR_EARLY
 142 #define CFG_SYS_CSPR2_FINAL             CFG_SYS_NOR0_CSPR
 143 #define CFG_SYS_AMASK2          CFG_SYS_NOR_AMASK
 144 #define CFG_SYS_CSOR2           CFG_SYS_NOR_CSOR
 145 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NOR_FTIM0
 146 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NOR_FTIM1
 147 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NOR_FTIM2
 148 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NOR_FTIM3
 149 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 150 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 151 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 152 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 153 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 154 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 155 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 156 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 157
 158 #define CFG_SYS_NAND_U_BOOT_SIZE        (512 * 1024)
 159 #else
 160 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 161 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR_EARLY
 162 #define CFG_SYS_CSPR0_FINAL             CFG_SYS_NOR0_CSPR
 163 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 164 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 165 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 166 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 167 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 168 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 169 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 170 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 171 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 172 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 173 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 174 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 175 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 176 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 177 #endif
 178 #endif
 179 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 180
 181 #ifdef CONFIG_TARGET_LS2081ARDB
 182 #define QIXIS_QMAP_MASK                 0x07
 183 #define QIXIS_QMAP_SHIFT                5
 184 #define QIXIS_LBMAP_DFLTBANK            0x00
 185 #define QIXIS_LBMAP_QSPI                0x00
 186 #define QIXIS_RCW_SRC_QSPI              0x62
 187 #define QIXIS_LBMAP_ALTBANK             0x20
 188 #define QIXIS_RST_CTL_RESET             0x31
 189 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 190 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 191 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 192 #define QIXIS_LBMAP_MASK                0x0f
 193 #define QIXIS_RST_CTL_RESET_EN          0x30
 194 #endif
 195
 196 /*
 197  * I2C
 198  */
 199 #ifdef CONFIG_TARGET_LS2081ARDB
 200 #define CFG_SYS_I2C_FPGA_ADDR   0x66
 201 #endif
 202 #define I2C_MUX_PCA_ADDR                0x75
 203 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 204
 205 /* I2C bus multiplexer */
 206 #define I2C_MUX_CH_DEFAULT      0x8
 207
 208 /* SPI */
 209
 210 /*
 211  * RTC configuration
 212  */
 213 #ifdef CONFIG_TARGET_LS2081ARDB
 214 #define CFG_SYS_I2C_RTC_ADDR         0x51
 215 #else
 216 #define CFG_SYS_I2C_RTC_ADDR         0x68
 217 #endif
 218
 219 #define BOOT_TARGET_DEVICES(func) \
 220         func(USB, usb, 0) \
 221         func(MMC, mmc, 0) \
 222         func(SCSI, scsi, 0) \
 223         func(DHCP, dhcp, na)
 224 #include <config_distro_bootcmd.h>
 225
 226 #ifdef CONFIG_TFABOOT
 227 #define QSPI_MC_INIT_CMD                                \
 228         "sf probe 0:0; "                                \
 229         "sf read 0x80640000 0x640000 0x80000; "         \
 230         "env exists secureboot && "                     \
 231         "esbc_validate 0x80640000 && "                  \
 232         "esbc_validate 0x80680000; "                    \
 233         "sf read 0x80a00000 0xa00000 0x200000; "        \
 234         "sf read 0x80e00000 0xe00000 0x100000; "        \
 235         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 236 #define SD_MC_INIT_CMD                          \
 237         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 238         "mmc read 0x80e00000 0x7000 0x800;"     \
 239         "env exists secureboot && "             \
 240         "mmc read 0x80640000 0x3200 0x20 && "   \
 241         "mmc read 0x80680000 0x3400 0x20 && "   \
 242         "esbc_validate 0x80640000 && "          \
 243         "esbc_validate 0x80680000 ;"            \
 244         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 245 #define IFC_MC_INIT_CMD                         \
 246         "env exists secureboot && "     \
 247         "esbc_validate 0x580640000 && "         \
 248         "esbc_validate 0x580680000; "           \
 249         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 250 #else
 251 #ifdef CONFIG_QSPI_BOOT
 252 #define MC_INIT_CMD                                     \
 253         "mcinitcmd=sf probe 0:0; "                      \
 254         "sf read 0x80640000 0x640000 0x80000; "         \
 255         "env exists secureboot && "                     \
 256         "esbc_validate 0x80640000 && "                  \
 257         "esbc_validate 0x80680000; "                    \
 258         "sf read 0x80a00000 0xa00000 0x200000; "        \
 259         "sf read 0x80e00000 0xe00000 0x100000; "        \
 260         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 261 #elif defined(CONFIG_SD_BOOT)
 262 #define MC_INIT_CMD                             \
 263         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 264         "mmc read 0x80e00000 0x7000 0x800;"     \
 265         "env exists secureboot && "             \
 266         "mmc read 0x80640000 0x3200 0x20 && "   \
 267         "mmc read 0x80680000 0x3400 0x20 && "   \
 268         "esbc_validate 0x80640000 && "          \
 269         "esbc_validate 0x80680000 ;"            \
 270         "fsl_mc start mc 0x80a00000 0x80e00000\0" \
 271         "mcmemsize=0x70000000\0"
 272 #else
 273 #define MC_INIT_CMD                             \
 274         "mcinitcmd=env exists secureboot && "   \
 275         "esbc_validate 0x580640000 && "         \
 276         "esbc_validate 0x580680000; "           \
 277         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 278 #endif
 279 #endif
 280
 281 /* Initial environment variables */
 282 #undef CONFIG_EXTRA_ENV_SETTINGS
 283 #ifdef CONFIG_TFABOOT
 284 #define CONFIG_EXTRA_ENV_SETTINGS               \
 285         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 286         "ramdisk_addr=0x800000\0"               \
 287         "ramdisk_size=0x2000000\0"              \
 288         "fdt_high=0xa0000000\0"                 \
 289         "initrd_high=0xffffffffffffffff\0"      \
 290         "kernel_addr=0x581000000\0"             \
 291         "kernel_start=0x1000000\0"              \
 292         "kernelheader_start=0x800000\0"         \
 293         "scriptaddr=0x80000000\0"               \
 294         "scripthdraddr=0x80080000\0"            \
 295         "fdtheader_addr_r=0x80100000\0"         \
 296         "kernelheader_addr_r=0x80200000\0"      \
 297         "kernelheader_addr=0x580600000\0"       \
 298         "kernel_addr_r=0x81000000\0"            \
 299         "kernelheader_size=0x40000\0"           \
 300         "fdt_addr_r=0x90000000\0"               \
 301         "load_addr=0xa0000000\0"                \
 302         "kernel_size=0x2800000\0"               \
 303         "kernel_addr_sd=0x8000\0"               \
 304         "kernel_size_sd=0x14000\0"              \
 305         "console=ttyAMA0,38400n8\0"             \
 306         "mcmemsize=0x70000000\0"                \
 307         "sd_bootcmd=echo Trying load from SD ..;" \
 308         "mmcinfo; mmc read $load_addr "         \
 309         "$kernel_addr_sd $kernel_size_sd && "   \
 310         "bootm $load_addr#$board\0"             \
 311         QSPI_MC_INIT_CMD                                \
 312         BOOTENV                                 \
 313         "boot_scripts=ls2088ardb_boot.scr\0"    \
 314         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 315         "scan_dev_for_boot_part="               \
 316                 "part list ${devtype} ${devnum} devplist; "     \
 317                 "env exists devplist || setenv devplist 1; "    \
 318                 "for distro_bootpart in ${devplist}; do "       \
 319                         "if fstype ${devtype} "                 \
 320                                 "${devnum}:${distro_bootpart} " \
 321                                 "bootfstype; then "             \
 322                                 "run scan_dev_for_boot; "       \
 323                         "fi; "                                  \
 324                 "done\0"                                        \
 325         "boot_a_script="                                        \
 326                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 327                         "${scriptaddr} ${prefix}${script}; "    \
 328                 "env exists secureboot && load ${devtype} "     \
 329                         "${devnum}:${distro_bootpart} "         \
 330                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 331                         "&& esbc_validate ${scripthdraddr};"    \
 332                 "source ${scriptaddr}\0"                        \
 333         "qspi_bootcmd=echo Trying load from qspi..;"            \
 334                 "sf probe && sf read $load_addr "               \
 335                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 336                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 337                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 338                 " bootm $load_addr#$board\0"                    \
 339         "nor_bootcmd=echo Trying load from nor..;"              \
 340                 "cp.b $kernel_addr $load_addr "                 \
 341                 "$kernel_size ; env exists secureboot && "      \
 342                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 343                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 344                 "bootm $load_addr#$board\0"
 345 #else
 346 #define CONFIG_EXTRA_ENV_SETTINGS               \
 347         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 348         "ramdisk_addr=0x800000\0"               \
 349         "ramdisk_size=0x2000000\0"              \
 350         "fdt_high=0xa0000000\0"                 \
 351         "initrd_high=0xffffffffffffffff\0"      \
 352         "kernel_addr=0x581000000\0"             \
 353         "kernel_start=0x1000000\0"              \
 354         "kernelheader_start=0x600000\0"         \
 355         "scriptaddr=0x80000000\0"               \
 356         "scripthdraddr=0x80080000\0"            \
 357         "fdtheader_addr_r=0x80100000\0"         \
 358         "kernelheader_addr_r=0x80200000\0"      \
 359         "kernelheader_addr=0x580600000\0"       \
 360         "kernel_addr_r=0x81000000\0"            \
 361         "kernelheader_size=0x40000\0"           \
 362         "fdt_addr_r=0x90000000\0"               \
 363         "load_addr=0xa0000000\0"                \
 364         "kernel_size=0x2800000\0"               \
 365         "kernel_addr_sd=0x8000\0"               \
 366         "kernel_size_sd=0x14000\0"              \
 367         "console=ttyAMA0,38400n8\0"             \
 368         "mcmemsize=0x70000000\0"                \
 369         "sd_bootcmd=echo Trying load from SD ..;" \
 370         "mmcinfo; mmc read $load_addr "         \
 371         "$kernel_addr_sd $kernel_size_sd && "   \
 372         "bootm $load_addr#$board\0"             \
 373         MC_INIT_CMD                             \
 374         BOOTENV                                 \
 375         "boot_scripts=ls2088ardb_boot.scr\0"    \
 376         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 377         "scan_dev_for_boot_part="               \
 378                 "part list ${devtype} ${devnum} devplist; "     \
 379                 "env exists devplist || setenv devplist 1; "    \
 380                 "for distro_bootpart in ${devplist}; do "       \
 381                         "if fstype ${devtype} "                 \
 382                                 "${devnum}:${distro_bootpart} " \
 383                                 "bootfstype; then "             \
 384                                 "run scan_dev_for_boot; "       \
 385                         "fi; "                                  \
 386                 "done\0"                                        \
 387         "boot_a_script="                                        \
 388                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 389                         "${scriptaddr} ${prefix}${script}; "    \
 390                 "env exists secureboot && load ${devtype} "     \
 391                         "${devnum}:${distro_bootpart} "         \
 392                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 393                         "env exists secureboot "        \
 394                         "&& esbc_validate ${scripthdraddr};"    \
 395                 "source ${scriptaddr}\0"                        \
 396         "qspi_bootcmd=echo Trying load from qspi..;"            \
 397                 "sf probe && sf read $load_addr "               \
 398                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 399                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 400                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 401                 " bootm $load_addr#$board\0"                    \
 402         "nor_bootcmd=echo Trying load from nor..;"              \
 403                 "cp.b $kernel_addr $load_addr "                 \
 404                 "$kernel_size ; env exists secureboot && "      \
 405                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 406                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 407                 "bootm $load_addr#$board\0"
 408 #endif
 409
 410 #ifdef CONFIG_TFABOOT
 411 #define QSPI_NOR_BOOTCOMMAND                                            \
 412                         "sf probe 0:0; "                                \
 413                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 414                         "env exists mcinitcmd && env exists secureboot "\
 415                         "&& esbc_validate 0x806c0000; "                 \
 416                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 417                         "env exists mcinitcmd && "                      \
 418                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 419                         "run distro_bootcmd;run qspi_bootcmd; "         \
 420                         "env exists secureboot && esbc_halt;"
 421
 422 /* Try to boot an on-SD kernel first, then do normal distro boot */
 423 #define SD_BOOTCOMMAND                                          \
 424                         "env exists mcinitcmd && env exists secureboot "\
 425                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 426                         "&& esbc_validate $load_addr; "                 \
 427                         "env exists mcinitcmd && run mcinitcmd "        \
 428                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 429                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 430                         "run distro_bootcmd;run sd_bootcmd; "           \
 431                         "env exists secureboot && esbc_halt;"
 432
 433 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 434 #define IFC_NOR_BOOTCOMMAND                                             \
 435                         "env exists mcinitcmd && env exists secureboot "\
 436                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 437                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 438                         "run distro_bootcmd;run nor_bootcmd; "          \
 439                         "env exists secureboot && esbc_halt;"
 440 #else
 441 #ifdef CONFIG_QSPI_BOOT
 442 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 443 #elif defined(CONFIG_SD_BOOT)
 444 /* Try to boot an on-SD kernel first, then do normal distro boot */
 445 #else
 446 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 447 #endif
 448 #endif
 449
 450 /* MAC/PHY configuration */
 451 #define CORTINA_PHY_ADDR1       0x10
 452 #define CORTINA_PHY_ADDR2       0x11
 453 #define CORTINA_PHY_ADDR3       0x12
 454 #define CORTINA_PHY_ADDR4       0x13
 455 #define AQ_PHY_ADDR1            0x00
 456 #define AQ_PHY_ADDR2            0x01
 457 #define AQ_PHY_ADDR3            0x02
 458 #define AQ_PHY_ADDR4            0x03
 459 #define AQR405_IRQ_MASK         0x36
 460
 461 #include <asm/fsl_secure_boot.h>
 462
 463 #endif /* __LS2_RDB_H */