include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #ifdef CONFIG_TARGET_LS2081ARDB
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16 #endif
  17
  18 #define I2C_MUX_CH_VOL_MONITOR          0xa
  19 #define I2C_VOL_MONITOR_ADDR            0x38
  20
  21 /* step the IR regulator in 5mV increments */
  22 #define IR_VDD_STEP_DOWN                5
  23 #define IR_VDD_STEP_UP                  5
  24 /* The lowest and highest voltage allowed for LS2080ARDB */
  25 #define VDD_MV_MIN                      819
  26 #define VDD_MV_MAX                      1212
  27
  28 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  29
  30 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  31 #define SPD_EEPROM_ADDRESS1     0x51
  32 #define SPD_EEPROM_ADDRESS2     0x52
  33 #define SPD_EEPROM_ADDRESS3     0x53
  34 #define SPD_EEPROM_ADDRESS4     0x54
  35 #define SPD_EEPROM_ADDRESS5     0x55
  36 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  37 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  38 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  39 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  40 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  41 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  42 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  43 #endif
  44
  45 /* SATA */
  46 #define CONFIG_SCSI_AHCI_PLAT
  47
  48 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  49 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  50
  51 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  52 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  53 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  54                                                 CONFIG_SYS_SCSI_MAX_LUN)
  55
  56 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  57
  58 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  59 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  60 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  61
  62 #define CONFIG_SYS_NOR0_CSPR                                    \
  63         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  64         CSPR_PORT_SIZE_16                                       | \
  65         CSPR_MSEL_NOR                                           | \
  66         CSPR_V)
  67 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  68         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  69         CSPR_PORT_SIZE_16                                       | \
  70         CSPR_MSEL_NOR                                           | \
  71         CSPR_V)
  72 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  73 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  74                                 FTIM0_NOR_TEADC(0x5) | \
  75                                 FTIM0_NOR_TEAHC(0x5))
  76 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  77                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  78                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  79 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  80                                 FTIM2_NOR_TCH(0x4) | \
  81                                 FTIM2_NOR_TWPH(0x0E) | \
  82                                 FTIM2_NOR_TWP(0x1c))
  83 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  84 #define CONFIG_SYS_IFC_CCR      0x01000000
  85
  86 #ifdef CONFIG_MTD_NOR_FLASH
  87 #define CONFIG_SYS_FLASH_QUIET_TEST
  88 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  89
  90 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  91 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  92 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  93 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  94
  95 #define CONFIG_SYS_FLASH_EMPTY_INFO
  96 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  97                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  98 #endif
  99
 100 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 101 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 102
 103 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 104 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 105                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 106                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 107                                 | CSPR_V)
 108 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 109
 110 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 111                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 112                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 113                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 114                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 115                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 116                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 117
 118 /* ONFI NAND Flash mode0 Timing Params */
 119 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 120                                         FTIM0_NAND_TWP(0x30)   | \
 121                                         FTIM0_NAND_TWCHT(0x0e) | \
 122                                         FTIM0_NAND_TWH(0x14))
 123 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 124                                         FTIM1_NAND_TWBE(0xab)  | \
 125                                         FTIM1_NAND_TRR(0x1c)   | \
 126                                         FTIM1_NAND_TRP(0x30))
 127 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 128                                         FTIM2_NAND_TREH(0x14) | \
 129                                         FTIM2_NAND_TWHRE(0x3c))
 130 #define CONFIG_SYS_NAND_FTIM3           0x0
 131
 132 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 133 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 134 #define CONFIG_MTD_NAND_VERIFY_WRITE
 135
 136 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 137 #define QIXIS_LBMAP_SWITCH              0x06
 138 #define QIXIS_LBMAP_MASK                0x0f
 139 #define QIXIS_LBMAP_SHIFT               0
 140 #define QIXIS_LBMAP_DFLTBANK            0x00
 141 #define QIXIS_LBMAP_ALTBANK             0x04
 142 #define QIXIS_LBMAP_NAND                0x09
 143 #define QIXIS_RST_CTL_RESET             0x31
 144 #define QIXIS_RST_CTL_RESET_EN          0x30
 145 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 146 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 147 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 148 #define QIXIS_RCW_SRC_NAND              0x119
 149 #define QIXIS_RST_FORCE_MEM             0x01
 150
 151 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 152 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 153                                 | CSPR_PORT_SIZE_8 \
 154                                 | CSPR_MSEL_GPCM \
 155                                 | CSPR_V)
 156 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 157                                 | CSPR_PORT_SIZE_8 \
 158                                 | CSPR_MSEL_GPCM \
 159                                 | CSPR_V)
 160
 161 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 162 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 163 /* QIXIS Timing parameters for IFC CS3 */
 164 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 165                                         FTIM0_GPCM_TEADC(0x0e) | \
 166                                         FTIM0_GPCM_TEAHC(0x0e))
 167 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 168                                         FTIM1_GPCM_TRAD(0x3f))
 169 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 170                                         FTIM2_GPCM_TCH(0xf) | \
 171                                         FTIM2_GPCM_TWP(0x3E))
 172 #define CONFIG_SYS_CS3_FTIM3            0x0
 173
 174 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
 175 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 176 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 177 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 178 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 179 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 180 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 181 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 182 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 183 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 184 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 185 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 186 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 187 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 188 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 189 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 190 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 191 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 192
 193 #define CONFIG_SPL_PAD_TO               0x80000
 194 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 195 #else
 196 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 197 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 198 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 199 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 200 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 201 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 202 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 203 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 204 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 205 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 206 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 207 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 208 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 209 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 210 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 211 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 212 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 213 #endif
 214
 215 /* Debug Server firmware */
 216 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 217 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 218 #endif
 219 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 220
 221 #ifdef CONFIG_TARGET_LS2081ARDB
 222 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 223 #define QIXIS_QMAP_MASK                 0x07
 224 #define QIXIS_QMAP_SHIFT                5
 225 #define QIXIS_LBMAP_DFLTBANK            0x00
 226 #define QIXIS_LBMAP_QSPI                0x00
 227 #define QIXIS_RCW_SRC_QSPI              0x62
 228 #define QIXIS_LBMAP_ALTBANK             0x20
 229 #define QIXIS_RST_CTL_RESET             0x31
 230 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 231 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 232 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 233 #define QIXIS_LBMAP_MASK                0x0f
 234 #define QIXIS_RST_CTL_RESET_EN          0x30
 235 #endif
 236
 237 /*
 238  * I2C
 239  */
 240 #ifdef CONFIG_TARGET_LS2081ARDB
 241 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 242 #endif
 243 #define I2C_MUX_PCA_ADDR                0x75
 244 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 245
 246 /* I2C bus multiplexer */
 247 #define I2C_MUX_CH_DEFAULT      0x8
 248
 249 /* SPI */
 250
 251 /*
 252  * RTC configuration
 253  */
 254 #define RTC
 255 #ifdef CONFIG_TARGET_LS2081ARDB
 256 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 257 #else
 258 #define CONFIG_RTC_DS3231               1
 259 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 260 #endif
 261
 262 /* EEPROM */
 263 #define CONFIG_SYS_I2C_EEPROM_NXID
 264 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 265
 266 #define CONFIG_FSL_MEMAC
 267
 268 #ifdef CONFIG_PCI
 269 #define CONFIG_PCI_SCAN_SHOW
 270 #endif
 271
 272 #define BOOT_TARGET_DEVICES(func) \
 273         func(USB, usb, 0) \
 274         func(MMC, mmc, 0) \
 275         func(SCSI, scsi, 0) \
 276         func(DHCP, dhcp, na)
 277 #include <config_distro_bootcmd.h>
 278
 279 #ifdef CONFIG_TFABOOT
 280 #define QSPI_MC_INIT_CMD                                \
 281         "sf probe 0:0; "                                \
 282         "sf read 0x80640000 0x640000 0x80000; "         \
 283         "env exists secureboot && "                     \
 284         "esbc_validate 0x80640000 && "                  \
 285         "esbc_validate 0x80680000; "                    \
 286         "sf read 0x80a00000 0xa00000 0x200000; "        \
 287         "sf read 0x80e00000 0xe00000 0x100000; "        \
 288         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 289 #define SD_MC_INIT_CMD                          \
 290         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 291         "mmc read 0x80e00000 0x7000 0x800;"     \
 292         "env exists secureboot && "             \
 293         "mmc read 0x80640000 0x3200 0x20 && "   \
 294         "mmc read 0x80680000 0x3400 0x20 && "   \
 295         "esbc_validate 0x80640000 && "          \
 296         "esbc_validate 0x80680000 ;"            \
 297         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 298 #define IFC_MC_INIT_CMD                         \
 299         "env exists secureboot && "     \
 300         "esbc_validate 0x580640000 && "         \
 301         "esbc_validate 0x580680000; "           \
 302         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 303 #else
 304 #ifdef CONFIG_QSPI_BOOT
 305 #define MC_INIT_CMD                                     \
 306         "mcinitcmd=sf probe 0:0; "                      \
 307         "sf read 0x80640000 0x640000 0x80000; "         \
 308         "env exists secureboot && "                     \
 309         "esbc_validate 0x80640000 && "                  \
 310         "esbc_validate 0x80680000; "                    \
 311         "sf read 0x80a00000 0xa00000 0x200000; "        \
 312         "sf read 0x80e00000 0xe00000 0x100000; "        \
 313         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 314 #elif defined(CONFIG_SD_BOOT)
 315 #define MC_INIT_CMD                             \
 316         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 317         "mmc read 0x80e00000 0x7000 0x800;"     \
 318         "env exists secureboot && "             \
 319         "mmc read 0x80640000 0x3200 0x20 && "   \
 320         "mmc read 0x80680000 0x3400 0x20 && "   \
 321         "esbc_validate 0x80640000 && "          \
 322         "esbc_validate 0x80680000 ;"            \
 323         "fsl_mc start mc 0x80a00000 0x80e00000\0" \
 324         "mcmemsize=0x70000000\0"
 325 #else
 326 #define MC_INIT_CMD                             \
 327         "mcinitcmd=env exists secureboot && "   \
 328         "esbc_validate 0x580640000 && "         \
 329         "esbc_validate 0x580680000; "           \
 330         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 331 #endif
 332 #endif
 333
 334 /* Initial environment variables */
 335 #undef CONFIG_EXTRA_ENV_SETTINGS
 336 #ifdef CONFIG_TFABOOT
 337 #define CONFIG_EXTRA_ENV_SETTINGS               \
 338         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 339         "ramdisk_addr=0x800000\0"               \
 340         "ramdisk_size=0x2000000\0"              \
 341         "fdt_high=0xa0000000\0"                 \
 342         "initrd_high=0xffffffffffffffff\0"      \
 343         "fdt_addr=0x64f00000\0"                 \
 344         "kernel_addr=0x581000000\0"             \
 345         "kernel_start=0x1000000\0"              \
 346         "kernelheader_start=0x800000\0"         \
 347         "scriptaddr=0x80000000\0"               \
 348         "scripthdraddr=0x80080000\0"            \
 349         "fdtheader_addr_r=0x80100000\0"         \
 350         "kernelheader_addr_r=0x80200000\0"      \
 351         "kernelheader_addr=0x580600000\0"       \
 352         "kernel_addr_r=0x81000000\0"            \
 353         "kernelheader_size=0x40000\0"           \
 354         "fdt_addr_r=0x90000000\0"               \
 355         "load_addr=0xa0000000\0"                \
 356         "kernel_size=0x2800000\0"               \
 357         "kernel_addr_sd=0x8000\0"               \
 358         "kernel_size_sd=0x14000\0"              \
 359         "console=ttyAMA0,38400n8\0"             \
 360         "mcmemsize=0x70000000\0"                \
 361         "sd_bootcmd=echo Trying load from SD ..;" \
 362         "mmcinfo; mmc read $load_addr "         \
 363         "$kernel_addr_sd $kernel_size_sd && "   \
 364         "bootm $load_addr#$board\0"             \
 365         QSPI_MC_INIT_CMD                                \
 366         BOOTENV                                 \
 367         "boot_scripts=ls2088ardb_boot.scr\0"    \
 368         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 369         "scan_dev_for_boot_part="               \
 370                 "part list ${devtype} ${devnum} devplist; "     \
 371                 "env exists devplist || setenv devplist 1; "    \
 372                 "for distro_bootpart in ${devplist}; do "       \
 373                         "if fstype ${devtype} "                 \
 374                                 "${devnum}:${distro_bootpart} " \
 375                                 "bootfstype; then "             \
 376                                 "run scan_dev_for_boot; "       \
 377                         "fi; "                                  \
 378                 "done\0"                                        \
 379         "boot_a_script="                                        \
 380                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 381                         "${scriptaddr} ${prefix}${script}; "    \
 382                 "env exists secureboot && load ${devtype} "     \
 383                         "${devnum}:${distro_bootpart} "         \
 384                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 385                         "&& esbc_validate ${scripthdraddr};"    \
 386                 "source ${scriptaddr}\0"                        \
 387         "qspi_bootcmd=echo Trying load from qspi..;"            \
 388                 "sf probe && sf read $load_addr "               \
 389                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 390                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 391                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 392                 " bootm $load_addr#$board\0"                    \
 393         "nor_bootcmd=echo Trying load from nor..;"              \
 394                 "cp.b $kernel_addr $load_addr "                 \
 395                 "$kernel_size ; env exists secureboot && "      \
 396                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 397                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 398                 "bootm $load_addr#$board\0"
 399 #else
 400 #define CONFIG_EXTRA_ENV_SETTINGS               \
 401         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 402         "ramdisk_addr=0x800000\0"               \
 403         "ramdisk_size=0x2000000\0"              \
 404         "fdt_high=0xa0000000\0"                 \
 405         "initrd_high=0xffffffffffffffff\0"      \
 406         "fdt_addr=0x64f00000\0"                 \
 407         "kernel_addr=0x581000000\0"             \
 408         "kernel_start=0x1000000\0"              \
 409         "kernelheader_start=0x600000\0"         \
 410         "scriptaddr=0x80000000\0"               \
 411         "scripthdraddr=0x80080000\0"            \
 412         "fdtheader_addr_r=0x80100000\0"         \
 413         "kernelheader_addr_r=0x80200000\0"      \
 414         "kernelheader_addr=0x580600000\0"       \
 415         "kernel_addr_r=0x81000000\0"            \
 416         "kernelheader_size=0x40000\0"           \
 417         "fdt_addr_r=0x90000000\0"               \
 418         "load_addr=0xa0000000\0"                \
 419         "kernel_size=0x2800000\0"               \
 420         "kernel_addr_sd=0x8000\0"               \
 421         "kernel_size_sd=0x14000\0"              \
 422         "console=ttyAMA0,38400n8\0"             \
 423         "mcmemsize=0x70000000\0"                \
 424         "sd_bootcmd=echo Trying load from SD ..;" \
 425         "mmcinfo; mmc read $load_addr "         \
 426         "$kernel_addr_sd $kernel_size_sd && "   \
 427         "bootm $load_addr#$board\0"             \
 428         MC_INIT_CMD                             \
 429         BOOTENV                                 \
 430         "boot_scripts=ls2088ardb_boot.scr\0"    \
 431         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 432         "scan_dev_for_boot_part="               \
 433                 "part list ${devtype} ${devnum} devplist; "     \
 434                 "env exists devplist || setenv devplist 1; "    \
 435                 "for distro_bootpart in ${devplist}; do "       \
 436                         "if fstype ${devtype} "                 \
 437                                 "${devnum}:${distro_bootpart} " \
 438                                 "bootfstype; then "             \
 439                                 "run scan_dev_for_boot; "       \
 440                         "fi; "                                  \
 441                 "done\0"                                        \
 442         "boot_a_script="                                        \
 443                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 444                         "${scriptaddr} ${prefix}${script}; "    \
 445                 "env exists secureboot && load ${devtype} "     \
 446                         "${devnum}:${distro_bootpart} "         \
 447                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 448                         "env exists secureboot "        \
 449                         "&& esbc_validate ${scripthdraddr};"    \
 450                 "source ${scriptaddr}\0"                        \
 451         "qspi_bootcmd=echo Trying load from qspi..;"            \
 452                 "sf probe && sf read $load_addr "               \
 453                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 454                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 455                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 456                 " bootm $load_addr#$board\0"                    \
 457         "nor_bootcmd=echo Trying load from nor..;"              \
 458                 "cp.b $kernel_addr $load_addr "                 \
 459                 "$kernel_size ; env exists secureboot && "      \
 460                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 461                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 462                 "bootm $load_addr#$board\0"
 463 #endif
 464
 465 #ifdef CONFIG_TFABOOT
 466 #define QSPI_NOR_BOOTCOMMAND                                            \
 467                         "sf probe 0:0; "                                \
 468                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 469                         "env exists mcinitcmd && env exists secureboot "\
 470                         "&& esbc_validate 0x806c0000; "                 \
 471                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 472                         "env exists mcinitcmd && "                      \
 473                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 474                         "run distro_bootcmd;run qspi_bootcmd; "         \
 475                         "env exists secureboot && esbc_halt;"
 476
 477 /* Try to boot an on-SD kernel first, then do normal distro boot */
 478 #define SD_BOOTCOMMAND                                          \
 479                         "env exists mcinitcmd && env exists secureboot "\
 480                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 481                         "&& esbc_validate $load_addr; "                 \
 482                         "env exists mcinitcmd && run mcinitcmd "        \
 483                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 484                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 485                         "run distro_bootcmd;run sd_bootcmd; "           \
 486                         "env exists secureboot && esbc_halt;"
 487
 488 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 489 #define IFC_NOR_BOOTCOMMAND                                             \
 490                         "env exists mcinitcmd && env exists secureboot "\
 491                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 492                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 493                         "run distro_bootcmd;run nor_bootcmd; "          \
 494                         "env exists secureboot && esbc_halt;"
 495 #else
 496 #ifdef CONFIG_QSPI_BOOT
 497 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 498 #elif defined(CONFIG_SD_BOOT)
 499 /* Try to boot an on-SD kernel first, then do normal distro boot */
 500 #else
 501 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 502 #endif
 503 #endif
 504
 505 /* MAC/PHY configuration */
 506 #define CORTINA_PHY_ADDR1       0x10
 507 #define CORTINA_PHY_ADDR2       0x11
 508 #define CORTINA_PHY_ADDR3       0x12
 509 #define CORTINA_PHY_ADDR4       0x13
 510 #define AQ_PHY_ADDR1            0x00
 511 #define AQ_PHY_ADDR2            0x01
 512 #define AQ_PHY_ADDR3            0x02
 513 #define AQ_PHY_ADDR4            0x03
 514 #define AQR405_IRQ_MASK         0x36
 515 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 516
 517 #include <asm/fsl_secure_boot.h>
 518
 519 #endif /* __LS2_RDB_H */