include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #ifdef CONFIG_TARGET_LS2081ARDB
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16 #endif
  17
  18 #define I2C_MUX_CH_VOL_MONITOR          0xa
  19 #define I2C_VOL_MONITOR_ADDR            0x38
  20
  21 /* step the IR regulator in 5mV increments */
  22 #define IR_VDD_STEP_DOWN                5
  23 #define IR_VDD_STEP_UP                  5
  24 /* The lowest and highest voltage allowed for LS2080ARDB */
  25 #define VDD_MV_MIN                      819
  26 #define VDD_MV_MAX                      1212
  27
  28 #ifndef __ASSEMBLY__
  29 unsigned long get_board_sys_clk(void);
  30 #endif
  31
  32 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  33 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  34
  35 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  36 #define SPD_EEPROM_ADDRESS1     0x51
  37 #define SPD_EEPROM_ADDRESS2     0x52
  38 #define SPD_EEPROM_ADDRESS3     0x53
  39 #define SPD_EEPROM_ADDRESS4     0x54
  40 #define SPD_EEPROM_ADDRESS5     0x55
  41 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  42 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  43 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  44 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  45 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  46 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  47 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  48 #endif
  49
  50 /* SATA */
  51 #define CONFIG_SCSI_AHCI_PLAT
  52
  53 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  54 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  55
  56 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  57 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  58 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  59                                                 CONFIG_SYS_SCSI_MAX_LUN)
  60
  61 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  62
  63 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  64 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  65 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  66
  67 #define CONFIG_SYS_NOR0_CSPR                                    \
  68         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  69         CSPR_PORT_SIZE_16                                       | \
  70         CSPR_MSEL_NOR                                           | \
  71         CSPR_V)
  72 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  73         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  74         CSPR_PORT_SIZE_16                                       | \
  75         CSPR_MSEL_NOR                                           | \
  76         CSPR_V)
  77 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  78 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  79                                 FTIM0_NOR_TEADC(0x5) | \
  80                                 FTIM0_NOR_TEAHC(0x5))
  81 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  82                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  83                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  84 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  85                                 FTIM2_NOR_TCH(0x4) | \
  86                                 FTIM2_NOR_TWPH(0x0E) | \
  87                                 FTIM2_NOR_TWP(0x1c))
  88 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  89 #define CONFIG_SYS_IFC_CCR      0x01000000
  90
  91 #ifdef CONFIG_MTD_NOR_FLASH
  92 #define CONFIG_SYS_FLASH_QUIET_TEST
  93 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  94
  95 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  96 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  97 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  98 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  99
 100 #define CONFIG_SYS_FLASH_EMPTY_INFO
 101 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 102                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 103 #endif
 104
 105 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 106 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 107
 108 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 109 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 110                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 111                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 112                                 | CSPR_V)
 113 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 114
 115 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 116                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 117                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 118                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 119                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 120                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 121                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 122
 123 /* ONFI NAND Flash mode0 Timing Params */
 124 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 125                                         FTIM0_NAND_TWP(0x30)   | \
 126                                         FTIM0_NAND_TWCHT(0x0e) | \
 127                                         FTIM0_NAND_TWH(0x14))
 128 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 129                                         FTIM1_NAND_TWBE(0xab)  | \
 130                                         FTIM1_NAND_TRR(0x1c)   | \
 131                                         FTIM1_NAND_TRP(0x30))
 132 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 133                                         FTIM2_NAND_TREH(0x14) | \
 134                                         FTIM2_NAND_TWHRE(0x3c))
 135 #define CONFIG_SYS_NAND_FTIM3           0x0
 136
 137 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 138 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 139 #define CONFIG_MTD_NAND_VERIFY_WRITE
 140
 141 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 142 #define QIXIS_LBMAP_SWITCH              0x06
 143 #define QIXIS_LBMAP_MASK                0x0f
 144 #define QIXIS_LBMAP_SHIFT               0
 145 #define QIXIS_LBMAP_DFLTBANK            0x00
 146 #define QIXIS_LBMAP_ALTBANK             0x04
 147 #define QIXIS_LBMAP_NAND                0x09
 148 #define QIXIS_RST_CTL_RESET             0x31
 149 #define QIXIS_RST_CTL_RESET_EN          0x30
 150 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 151 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 152 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 153 #define QIXIS_RCW_SRC_NAND              0x119
 154 #define QIXIS_RST_FORCE_MEM             0x01
 155
 156 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 157 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 158                                 | CSPR_PORT_SIZE_8 \
 159                                 | CSPR_MSEL_GPCM \
 160                                 | CSPR_V)
 161 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 162                                 | CSPR_PORT_SIZE_8 \
 163                                 | CSPR_MSEL_GPCM \
 164                                 | CSPR_V)
 165
 166 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 167 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 168 /* QIXIS Timing parameters for IFC CS3 */
 169 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 170                                         FTIM0_GPCM_TEADC(0x0e) | \
 171                                         FTIM0_GPCM_TEAHC(0x0e))
 172 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 173                                         FTIM1_GPCM_TRAD(0x3f))
 174 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 175                                         FTIM2_GPCM_TCH(0xf) | \
 176                                         FTIM2_GPCM_TWP(0x3E))
 177 #define CONFIG_SYS_CS3_FTIM3            0x0
 178
 179 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
 180 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 181 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 182 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 183 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 184 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 185 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 186 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 187 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 188 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 189 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 190 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 191 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 192 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 193 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 194 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 195 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 196 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 197
 198 #define CONFIG_SPL_PAD_TO               0x80000
 199 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 200 #else
 201 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 202 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 203 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 204 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 205 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 206 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 207 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 208 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 209 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 210 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 211 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 212 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 213 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 214 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 215 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 216 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 217 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 218 #endif
 219
 220 /* Debug Server firmware */
 221 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 222 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 223 #endif
 224 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 225
 226 #ifdef CONFIG_TARGET_LS2081ARDB
 227 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 228 #define QIXIS_QMAP_MASK                 0x07
 229 #define QIXIS_QMAP_SHIFT                5
 230 #define QIXIS_LBMAP_DFLTBANK            0x00
 231 #define QIXIS_LBMAP_QSPI                0x00
 232 #define QIXIS_RCW_SRC_QSPI              0x62
 233 #define QIXIS_LBMAP_ALTBANK             0x20
 234 #define QIXIS_RST_CTL_RESET             0x31
 235 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 236 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 237 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 238 #define QIXIS_LBMAP_MASK                0x0f
 239 #define QIXIS_RST_CTL_RESET_EN          0x30
 240 #endif
 241
 242 /*
 243  * I2C
 244  */
 245 #ifdef CONFIG_TARGET_LS2081ARDB
 246 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 247 #endif
 248 #define I2C_MUX_PCA_ADDR                0x75
 249 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 250
 251 /* I2C bus multiplexer */
 252 #define I2C_MUX_CH_DEFAULT      0x8
 253
 254 /* SPI */
 255
 256 /*
 257  * RTC configuration
 258  */
 259 #define RTC
 260 #ifdef CONFIG_TARGET_LS2081ARDB
 261 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 262 #else
 263 #define CONFIG_RTC_DS3231               1
 264 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 265 #endif
 266
 267 /* EEPROM */
 268 #define CONFIG_SYS_I2C_EEPROM_NXID
 269 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 270
 271 #define CONFIG_FSL_MEMAC
 272
 273 #ifdef CONFIG_PCI
 274 #define CONFIG_PCI_SCAN_SHOW
 275 #endif
 276
 277 #define BOOT_TARGET_DEVICES(func) \
 278         func(USB, usb, 0) \
 279         func(MMC, mmc, 0) \
 280         func(SCSI, scsi, 0) \
 281         func(DHCP, dhcp, na)
 282 #include <config_distro_bootcmd.h>
 283
 284 #ifdef CONFIG_TFABOOT
 285 #define QSPI_MC_INIT_CMD                                \
 286         "sf probe 0:0; "                                \
 287         "sf read 0x80640000 0x640000 0x80000; "         \
 288         "env exists secureboot && "                     \
 289         "esbc_validate 0x80640000 && "                  \
 290         "esbc_validate 0x80680000; "                    \
 291         "sf read 0x80a00000 0xa00000 0x200000; "        \
 292         "sf read 0x80e00000 0xe00000 0x100000; "        \
 293         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 294 #define SD_MC_INIT_CMD                          \
 295         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 296         "mmc read 0x80e00000 0x7000 0x800;"     \
 297         "env exists secureboot && "             \
 298         "mmc read 0x80640000 0x3200 0x20 && "   \
 299         "mmc read 0x80680000 0x3400 0x20 && "   \
 300         "esbc_validate 0x80640000 && "          \
 301         "esbc_validate 0x80680000 ;"            \
 302         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 303 #define IFC_MC_INIT_CMD                         \
 304         "env exists secureboot && "     \
 305         "esbc_validate 0x580640000 && "         \
 306         "esbc_validate 0x580680000; "           \
 307         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 308 #else
 309 #ifdef CONFIG_QSPI_BOOT
 310 #define MC_INIT_CMD                                     \
 311         "mcinitcmd=sf probe 0:0; "                      \
 312         "sf read 0x80640000 0x640000 0x80000; "         \
 313         "env exists secureboot && "                     \
 314         "esbc_validate 0x80640000 && "                  \
 315         "esbc_validate 0x80680000; "                    \
 316         "sf read 0x80a00000 0xa00000 0x200000; "        \
 317         "sf read 0x80e00000 0xe00000 0x100000; "        \
 318         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 319 #elif defined(CONFIG_SD_BOOT)
 320 #define MC_INIT_CMD                             \
 321         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 322         "mmc read 0x80e00000 0x7000 0x800;"     \
 323         "env exists secureboot && "             \
 324         "mmc read 0x80640000 0x3200 0x20 && "   \
 325         "mmc read 0x80680000 0x3400 0x20 && "   \
 326         "esbc_validate 0x80640000 && "          \
 327         "esbc_validate 0x80680000 ;"            \
 328         "fsl_mc start mc 0x80a00000 0x80e00000\0" \
 329         "mcmemsize=0x70000000\0"
 330 #else
 331 #define MC_INIT_CMD                             \
 332         "mcinitcmd=env exists secureboot && "   \
 333         "esbc_validate 0x580640000 && "         \
 334         "esbc_validate 0x580680000; "           \
 335         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 336 #endif
 337 #endif
 338
 339 /* Initial environment variables */
 340 #undef CONFIG_EXTRA_ENV_SETTINGS
 341 #ifdef CONFIG_TFABOOT
 342 #define CONFIG_EXTRA_ENV_SETTINGS               \
 343         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 344         "ramdisk_addr=0x800000\0"               \
 345         "ramdisk_size=0x2000000\0"              \
 346         "fdt_high=0xa0000000\0"                 \
 347         "initrd_high=0xffffffffffffffff\0"      \
 348         "fdt_addr=0x64f00000\0"                 \
 349         "kernel_addr=0x581000000\0"             \
 350         "kernel_start=0x1000000\0"              \
 351         "kernelheader_start=0x800000\0"         \
 352         "scriptaddr=0x80000000\0"               \
 353         "scripthdraddr=0x80080000\0"            \
 354         "fdtheader_addr_r=0x80100000\0"         \
 355         "kernelheader_addr_r=0x80200000\0"      \
 356         "kernelheader_addr=0x580600000\0"       \
 357         "kernel_addr_r=0x81000000\0"            \
 358         "kernelheader_size=0x40000\0"           \
 359         "fdt_addr_r=0x90000000\0"               \
 360         "load_addr=0xa0000000\0"                \
 361         "kernel_size=0x2800000\0"               \
 362         "kernel_addr_sd=0x8000\0"               \
 363         "kernel_size_sd=0x14000\0"              \
 364         "console=ttyAMA0,38400n8\0"             \
 365         "mcmemsize=0x70000000\0"                \
 366         "sd_bootcmd=echo Trying load from SD ..;" \
 367         "mmcinfo; mmc read $load_addr "         \
 368         "$kernel_addr_sd $kernel_size_sd && "   \
 369         "bootm $load_addr#$board\0"             \
 370         QSPI_MC_INIT_CMD                                \
 371         BOOTENV                                 \
 372         "boot_scripts=ls2088ardb_boot.scr\0"    \
 373         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 374         "scan_dev_for_boot_part="               \
 375                 "part list ${devtype} ${devnum} devplist; "     \
 376                 "env exists devplist || setenv devplist 1; "    \
 377                 "for distro_bootpart in ${devplist}; do "       \
 378                         "if fstype ${devtype} "                 \
 379                                 "${devnum}:${distro_bootpart} " \
 380                                 "bootfstype; then "             \
 381                                 "run scan_dev_for_boot; "       \
 382                         "fi; "                                  \
 383                 "done\0"                                        \
 384         "boot_a_script="                                        \
 385                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 386                         "${scriptaddr} ${prefix}${script}; "    \
 387                 "env exists secureboot && load ${devtype} "     \
 388                         "${devnum}:${distro_bootpart} "         \
 389                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 390                         "&& esbc_validate ${scripthdraddr};"    \
 391                 "source ${scriptaddr}\0"                        \
 392         "qspi_bootcmd=echo Trying load from qspi..;"            \
 393                 "sf probe && sf read $load_addr "               \
 394                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 395                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 396                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 397                 " bootm $load_addr#$board\0"                    \
 398         "nor_bootcmd=echo Trying load from nor..;"              \
 399                 "cp.b $kernel_addr $load_addr "                 \
 400                 "$kernel_size ; env exists secureboot && "      \
 401                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 402                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 403                 "bootm $load_addr#$board\0"
 404 #else
 405 #define CONFIG_EXTRA_ENV_SETTINGS               \
 406         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 407         "ramdisk_addr=0x800000\0"               \
 408         "ramdisk_size=0x2000000\0"              \
 409         "fdt_high=0xa0000000\0"                 \
 410         "initrd_high=0xffffffffffffffff\0"      \
 411         "fdt_addr=0x64f00000\0"                 \
 412         "kernel_addr=0x581000000\0"             \
 413         "kernel_start=0x1000000\0"              \
 414         "kernelheader_start=0x600000\0"         \
 415         "scriptaddr=0x80000000\0"               \
 416         "scripthdraddr=0x80080000\0"            \
 417         "fdtheader_addr_r=0x80100000\0"         \
 418         "kernelheader_addr_r=0x80200000\0"      \
 419         "kernelheader_addr=0x580600000\0"       \
 420         "kernel_addr_r=0x81000000\0"            \
 421         "kernelheader_size=0x40000\0"           \
 422         "fdt_addr_r=0x90000000\0"               \
 423         "load_addr=0xa0000000\0"                \
 424         "kernel_size=0x2800000\0"               \
 425         "kernel_addr_sd=0x8000\0"               \
 426         "kernel_size_sd=0x14000\0"              \
 427         "console=ttyAMA0,38400n8\0"             \
 428         "mcmemsize=0x70000000\0"                \
 429         "sd_bootcmd=echo Trying load from SD ..;" \
 430         "mmcinfo; mmc read $load_addr "         \
 431         "$kernel_addr_sd $kernel_size_sd && "   \
 432         "bootm $load_addr#$board\0"             \
 433         MC_INIT_CMD                             \
 434         BOOTENV                                 \
 435         "boot_scripts=ls2088ardb_boot.scr\0"    \
 436         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 437         "scan_dev_for_boot_part="               \
 438                 "part list ${devtype} ${devnum} devplist; "     \
 439                 "env exists devplist || setenv devplist 1; "    \
 440                 "for distro_bootpart in ${devplist}; do "       \
 441                         "if fstype ${devtype} "                 \
 442                                 "${devnum}:${distro_bootpart} " \
 443                                 "bootfstype; then "             \
 444                                 "run scan_dev_for_boot; "       \
 445                         "fi; "                                  \
 446                 "done\0"                                        \
 447         "boot_a_script="                                        \
 448                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 449                         "${scriptaddr} ${prefix}${script}; "    \
 450                 "env exists secureboot && load ${devtype} "     \
 451                         "${devnum}:${distro_bootpart} "         \
 452                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 453                         "env exists secureboot "        \
 454                         "&& esbc_validate ${scripthdraddr};"    \
 455                 "source ${scriptaddr}\0"                        \
 456         "qspi_bootcmd=echo Trying load from qspi..;"            \
 457                 "sf probe && sf read $load_addr "               \
 458                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 459                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 460                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 461                 " bootm $load_addr#$board\0"                    \
 462         "nor_bootcmd=echo Trying load from nor..;"              \
 463                 "cp.b $kernel_addr $load_addr "                 \
 464                 "$kernel_size ; env exists secureboot && "      \
 465                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 466                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 467                 "bootm $load_addr#$board\0"
 468 #endif
 469
 470 #ifdef CONFIG_TFABOOT
 471 #define QSPI_NOR_BOOTCOMMAND                                            \
 472                         "sf probe 0:0; "                                \
 473                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 474                         "env exists mcinitcmd && env exists secureboot "\
 475                         "&& esbc_validate 0x806c0000; "                 \
 476                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 477                         "env exists mcinitcmd && "                      \
 478                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 479                         "run distro_bootcmd;run qspi_bootcmd; "         \
 480                         "env exists secureboot && esbc_halt;"
 481
 482 /* Try to boot an on-SD kernel first, then do normal distro boot */
 483 #define SD_BOOTCOMMAND                                          \
 484                         "env exists mcinitcmd && env exists secureboot "\
 485                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 486                         "&& esbc_validate $load_addr; "                 \
 487                         "env exists mcinitcmd && run mcinitcmd "        \
 488                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 489                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 490                         "run distro_bootcmd;run sd_bootcmd; "           \
 491                         "env exists secureboot && esbc_halt;"
 492
 493 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 494 #define IFC_NOR_BOOTCOMMAND                                             \
 495                         "env exists mcinitcmd && env exists secureboot "\
 496                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 497                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 498                         "run distro_bootcmd;run nor_bootcmd; "          \
 499                         "env exists secureboot && esbc_halt;"
 500 #else
 501 #ifdef CONFIG_QSPI_BOOT
 502 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 503 #elif defined(CONFIG_SD_BOOT)
 504 /* Try to boot an on-SD kernel first, then do normal distro boot */
 505 #else
 506 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 507 #endif
 508 #endif
 509
 510 /* MAC/PHY configuration */
 511 #define CORTINA_PHY_ADDR1       0x10
 512 #define CORTINA_PHY_ADDR2       0x11
 513 #define CORTINA_PHY_ADDR3       0x12
 514 #define CORTINA_PHY_ADDR4       0x13
 515 #define AQ_PHY_ADDR1            0x00
 516 #define AQ_PHY_ADDR2            0x01
 517 #define AQ_PHY_ADDR3            0x02
 518 #define AQ_PHY_ADDR4            0x03
 519 #define AQR405_IRQ_MASK         0x36
 520 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 521
 522 #include <asm/fsl_secure_boot.h>
 523
 524 #endif /* __LS2_RDB_H */